An EEPROM includes an array of memory cells divided into a plurality of memory blocks in a semiconductor well region in a substrate. Each block includes series arrays of FATMOS transistors each acting as one memory cell, wherein binary information may be stored in a selected cell transistor by...
An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks, in each block, erase pu... T Nakayama,S.-I. Kobayashi,Y Miyawaki,... - IEEE Journal of Solid-State Circuits 被引量: 116发表: 1991年 EEPROM decoder ...
The memory cells of the Flash EEPROM are partitioned into a plurality of sectors that individually are erasable together as a unit. The individual sectors are provided with a user data portion and an overhead portion which allow for operations similar to that of a magnetic disk drive. In one...
US5581723 Feb 19, 1993 Dec 3, 1996 Intel Corporation Method and apparatus for retaining flash block structure data during erase operations in a flash EEPROM memory arrayUS5581723 1993年2月19日 1996年12月3日 Intel Corporation Method and apparatus for retaining flash block structure data during ...
Method and apparatus for retaining flash block structure data during erase operations in a flash EEPROM memory arrayA method for reliably storing management data in a flash EEPROM memory array, which array is divided into a plurality of individually-erasable blocks of memory cells and in which ...