A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices Article 14 December 2020 A computing-in-memory macro based on three-dimensional resistive random-access memory Article Open access 26 July 2022 A compute-in-memory chip based on resistive ...
A 1.041-Mb/mm2 27.38-TOPS/W signed-INT8 dynamic-logic-based ADC-less SRAM compute-in-memory macro in 28nm with reconfigurable bitwise operation for AI and embedded applications. In 2022 IEEE International Solid-State Circuits Conference 188–190 (IEEE, 2022); https://doi.org/10.1109/ISSCC...
et al. A 22 nm 2 Mb ReRAM compute-in-memory macro with 121-28TOPS/W for multibit MAC computing for tiny AI edge devices. In IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers 244–245 (IEEE, 2020). Tang, K.-T. et al. Considerations of ...
This paper demonstrates the first Monolithic 3D+-IC based Compute-in-Memory (CiM) Macro performing massively parallel beyond-Boolean operations targeting database and machine learning (ML) applications. The proposed CiM technique supports data filtering, sorting, and sparse matrix-matrix multiplication (...
This paper presents a 64Kb RRAM macro supporting: (1) a programmable (1 to 9) number of row-accesses (N) to enable vector-matrix multiplication (referred to as compute-in-memory, or CIM) for a target algorithm-level inference-accuracy [2] -[8], (2) voltage-based RD with active feed...
Su JW et al (2020) A 28nm 64kb inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips. In: IEEE international solid-state circuits conference (ISSCC) Google Scholar Sun X, Yu S (2019) Impact of non-ideal characteristics of resistive synaptic devices...
"The 6.6 megabit complementary metal–oxide–semiconductor (CMOS)-integrated macro uses 22 nm spin-transfer torque magnetic random-access memory technology," Chiu, Khwa and their colleagues explained in their paper. "The macro achieves high randomness (inter-Hamming distance, 0.4999) and high...
29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification (referred to as compute-in-memory, or CIM) for a target algorithm-level inference-accuracy [2] -[8], (2) voltage-based RD with active ...
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference Article10 August 2023 A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices ...
A computing-in-memory macro based on three-dimensional resistive random-access memory. Nat. Electron. 5, 469–477 (2022). Article Google Scholar He, K., Zhang, X., Ren, S. & Sun, J. Deep residual learning for image recognition. in 2016 IEEE Conference on Computer Vision and Pattern ...