MALI_DVFS_ENABLEDclk = mali_gpu_clk;#endif_mali_osk_lock_wait(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);if(mali_clk_get(bis_vpll) == MALI_FALSE)returnMALI_FALSE; rate = (unsignedlong)clk * (unsignedlong)mhz; MALI_DEBUG_PRINT(3,("=clk_set_rate: %d , %d \n",clk, mhz ));if(...
MALI_DEBUG_PRINT(3,("enable_mali_clocks mali_clock %p error %d \n", mali_clock, err));#if0#ifMALI_DVFS_ENABLED// set clock rateif(get_mali_dvfs_control_status() !=0|| mali_gpu_clk >= mali_runtime_resume.clk)mali_clk_set_rate(mali_gpu_clk, GPU_MHZ);else{ mali_regulator_set...
mddi_clk = clk_get(NULL,"mddi_clk");if(IS_ERR(mddi_clk)) { printk(KERN_ERR"can't find mddi_clk\n");returnPTR_ERR(mddi_clk); } ret =clk_set_min_rate(mddi_clk,49000000);if(ret) printk(KERN_ERR"Can't set mddi_clk min rate to 49000000\n"); printk(KERN_INFO"mddi_clk init...