MALI_DVFS_ENABLEDclk = mali_gpu_clk;#endif_mali_osk_lock_wait(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);if(mali_clk_get(bis_vpll) == MALI_FALSE)returnMALI_FALSE; rate = (unsignedlong)clk * (unsignedlong)mhz; MALI_DEBUG_PRINT(3,("=clk_set_rate: %d , %d \n",clk, mhz ));if(...
> its rate. But that clock actually has CLK_SET_RATE_PARENT flag set in > the clock driver [2]. So the right thing to do in this case (and > that's basically how it's done in Linux kernel too) is to traverse the > clock tree upwards, and try to find the parent capable to ...
ret = clk_set_rate(clk, PMC_CLK_RATE_19_2MHZ); if (ret) acpi_handle_err(adev->handle, "Error setting clk-rate for %s:%d\n", name, ret);clk_put(clk); return ret; }static int atomisp_csi2_get_port(struct acpi_device *adev) ...
.set_rate = apq8016_clk_set_rate, }; static const struct udevice_id gcc_apq8016_of_match[] = { { .compatible = "qcom,gcc-apq8016", /* TODO: add reset map */ .data = (ulong)&apq8016_clk_data, }, { } }; 33 changes: 27 additions & 6 deletions 33 drivers/clk/qcom/clock...
+ ret = clk_set_rate(host->fclk, mmc->f_max); + if (ret) { + dev_err(&pdev->dev, "failed to set clock to %d\n", mmc->f_max); goto err1; } -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in ...
}#elsemali_clk_set_rate((unsignedint)mali_gpu_clk, GPU_MHZ); maliDvfsStatus.currentStep = MALI_DVFS_DEFAULT_STEP;#endifMALI_SUCCESS; } 开发者ID:aramos1988,项目名称:Android_b2_Kernel,代码行数:26,代码来源:exynos4_pmm.c 示例2: set_mali_dvfs_status ...
void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, int div, int m, int n, int source) int div, int m, int n, int source, u8 mnd_width) { u32 cfg; /* M value for MND divider. */ @@ -92,11 +92,14 @@ void clk_rcg_set_rate_mnd(phys_addr_t...
The provider variable is already dereferenced earlier in this function. Drop the check for NULL as it is impossible. Found with smatch drivers/clk/tegra/clk-tegra210-emc.c:131 tegra210_clk_emc_set_rate() warn: variable dereferenced before check 'provider' (see line 124) Cc: Joseph Lo <jo...
> > its rate. But that clock actually has CLK_SET_RATE_PARENT flag set in > > the clock driver [2]. So the right thing to do in this case (and > > that's basically how it's done in Linux kernel too) is to traverse the ...
clk_set_rate(mfd->ebi1_clk, pm_qos_rate *1000); } clk_enable(mfd->ebi1_clk); }#endifmfd = platform_get_drvdata(pdev); mfd->fbi->var.pixclock = clk_round_rate(pixel_mdp_clk, mfd->fbi->var.pixclock); ret = clk_set_rate(pixel_mdp_clk, mfd->fbi->var.pixclock);if(ret...