}if(clk_set_rate(edp_drv->link_clk, edp_drv->link_rate *27000000) <0) pr_err("%s: link_clk -clk_set_ratefailed\n", __func__);if(clk_set_rate(edp_drv->aux_clk, edp_drv->aux_rate) <0) pr_err("%s: aux_clk -clk_set_ratefailed\n", __func__);if(clk_set_rate(edp...
long clk_round_rate(struct clk *clk, unsigned long rate) //获取时钟频率 unsigned long clk_get_rate(struct clk *clk) //设置时钟频率 int clk_set_rate(struct clk *clk, unsigned long rate) 准备/使能clk: /* 开时钟前调用,可能会造成休眠,所以把休眠部分放到这里,可以原子操作的放到enable里 */ ...
可以使用clk_register_mux()函数注册一个时钟选择器,在使用时可以通过clk_set_parent()函数设置该时钟的父时钟。 Divider Clock(时钟分频器):将输入时钟的频率分频后得到输出时钟。可以使用clk_register_divider()函数注册一个时钟分频器,在使用时可以通过clk_set_rate()函数设置该时钟的频率。 Fractional-N PLL Clo...
clk_set_rate() 函数最终将会调用clk节点对象的成员函数clk->set_rate() 设置时钟。 层次关系如下图所示: 驱动层 1. 驱动层与porting层之间的api 驱动层与porting层之间的api,定义在include/linux/clk.h文件中 // clk的结构体,空的, // 正真的实现在arch\arm\plat-vc088x\include\plat\clock.h struct...
ret = clk_set_rate(clkp, rounded_rate); 2. 例子:LCD clk 设置 LCD 时钟框图: 从图中可以清晰的看到,LCD functional clk有多个时钟src,实际使用的有PLL1624M,PLL1416M和PLL3,它有两个MUX,外部的MUX由APMU寄存器控制,决定是选择PLL1624M还是PLL1416M,然后通过内部寄存器LCD_SCLK_DIV在外部选择的clk src和...
Currently, it isn't possible to build clock drivers for more than one platform due to how the msm_enable() and msm_set_rate() callbacks are implemented. Extend qcom_clk_data to include function pointers for these and convert all platforms to use them. Previously, clock drivers relied on ...
mdp3_clk_set_rate(MDP3_CLK_VSYNC, MDP_VSYNC_CLK_RATE, MDP3_CLIENT_DMA_P); rc = mdp3_clk_prepare();if(rc) { pr_err("mdp3 clk prepare fail\n");returnrc; } rc =mdp3_clk_enable(1,1);if(rc) { pr_err("mdp3 clk enable fail\n"); ...
> its rate. But that clock actually has CLK_SET_RATE_PARENT flag set in > the clock driver [2]. So the right thing to do in this case (and > that's basically how it's done in Linux kernel too) is to traverse the > clock tree upwards, and try to find the parent capable to ...
.set_rate = rlx_set_rate, .set_parent = rlx_set_parent, .get_parent = rlx_get_parent, .recalc_rate = rlx_recalc, }; 1. 2. 3. 4. 5. 6. 7. 8. 9. 通过一个宏DEFINE_CLK_RLX将这个clk_ops赋值给struct clk结构体中的ops
int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id) { int ret = -EOPNOTSUPP; unsigned long flags; spin_lock_irqsave(&clock_lock, flags); if (likely(clk->ops && clk->ops->set_rate)) { ret = clk->ops->set_rate(clk, rate, algo_id); ret = clk->ops->...