long clk_round_rate(struct clk *clk, unsigned long rate) //获取时钟频率 unsigned long clk_get_rate(struct clk *clk) //设置时钟频率 int clk_set_rate(struct clk *clk, unsigned long rate) 准备/使能clk: /* 开时钟前调用,可能会造成休眠,所以把休眠部分放到这里,可以原子操作的放到enable里 */ ...
可以使用clk_register_mux()函数注册一个时钟选择器,在使用时可以通过clk_set_parent()函数设置该时钟的父时钟。 Divider Clock(时钟分频器):将输入时钟的频率分频后得到输出时钟。可以使用clk_register_divider()函数注册一个时钟分频器,在使用时可以通过clk_set_rate()函数设置该时钟的频率。 Fractional-N PLL Clo...
2、时钟使能与禁止:通过clk_enable和clk_disable函数控制clock的开关。 3、时钟频率设置:通过clk_set_rate函数设置clock的频率。 4、时钟父级关系管理:通过clk_set_parent函数设置clock的父级clock。 5、时钟状态查询:通过clk_get_rate和clk_is_enabled等函数查询clock的状态和频率。 四、时钟链表 在Linux中,所有的...
unsigned int set, clear; if (rate == clk->rate) return 0; new_rate = __clk_sel_mux_div(clk, rate, &mux, &div, &best_parent); if (1 == div) div = 0; set = (mux << clk->reg_data[SOURCE][CONTROL].reg_shift) | \ (div << clk->reg_data[DIV][CONTROL].reg_shift);...
clk_set_rate() 函数最终将会调用clk节点对象的成员函数clk->set_rate() 设置时钟。 层次关系如下图所示: 驱动层 1. 驱动层与porting层之间的api 驱动层与porting层之间的api,定义在include/linux/clk.h文件中 // clk的结构体,空的, // 正真的实现在arch\arm\plat-vc088x\include\plat\clock.h struct...
.set_rate = rlx_set_rate, .set_parent = rlx_set_parent, .get_parent = rlx_get_parent, .recalc_rate = rlx_recalc, }; 1. 2. 3. 4. 5. 6. 7. 8. 9. 通过一个宏DEFINE_CLK_RLX将这个clk_ops赋值给struct clk结构体中的ops
clk_set_rate_range() will use the last requested rate for the clock when it calls into the driver set_rate hook. However, if CLK_GET_RATE_NOCACHE is set on that clock, the last requested rate might not be matching the current rate of the clock. In such a case, let's read out ...
Clock rates are cached within the individual clock nodes, and right now if one changes a clock rate somewhere in the middle of the tree, none of its child clocks notice the change. To fix this, clear up all the cached rates for us and our child clocks. Signed-off-by: Tero Kristo <...
> > > > .set_rate capable parent is found, and use that parent to actually > > > > change the rate. The search will stop once the first .set_rate capable > > > > clock is found, which is usually enough to handle most cases. ...
你好，我在进行AD9361的配置上面出现了如下的问题：1.Calibration TIMEOUT (0x5E, 0x80)clk_set_rate...