@@ -1459,11 +1459,14 @@ static void clk_core_init_rate_req(struct clk_core * const core, { struct clk_core *parent;if (!core || WARN_ON(!req)) if (WARN_ON(!req)) return;memset(req, 0, sizeof(*req));if (!core)
@@ -471,7 +471,6 @@ void clk_free(struct clk *clk) ulong clk_get_rate(struct clk *clk) { const struct clk_ops *ops; int ret;debug("%s(clk=%p)\n", __func__, clk); if (!clk_valid(clk)) @@ -481,11 +480,7 @@ ulong clk_get_rate(struct clk *clk)if...
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> After DPLL has locked, the pulses are generated, and the average pulse rate is 128 x the sampling frequency.(For a 44.1 Khz input sampling frequency, the average pulse rate = 128 x 44.1 Khz.) When the SPDIF input is 44100Hz, 88200Hz, or 176400Hz, I want to get an outpu...
> > its rate. But that clock actually has CLK_SET_RATE_PARENT flag set in > > the clock driver [2]. So the right thing to do in this case (and > > that's basically how it's done in Linux kernel too) is to traverse the ...
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+ } + + ret = clk_set_rate(host->fclk, mmc->f_max); + if (ret) { + dev_err(&pdev->dev, "failed to set clock to %d\n", mmc->f_max); goto err1; } -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in ...
您好!ADC_CLK 是BBPLL的分频,CLK_OUT是ADC_CLK的整数分频,DATA_CLK是ADC_CLK经过抽取后输出的数据率,有三个HB滤波器和一个FIR滤波器,如果三个HB滤波器都是能,FIR抽取率为2,那么ADC_CLK就是DATA_CLK的16倍。因此,需要根据您需要的数据率,插值率/抽取率,得出ADC_CLK的频率进行设置。具体的RX Digital Filters...
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clkp = dev_get_clk_ptr(child_dev); clk_clean_rate_cache(clkp); } }ulong clk_set_rate(struct clk *clk, ulong rate) { const struct clk_ops *ops; @@ -580,6 +596,9 @@ ulong clk_set_rate(struct clk *clk, ulong rate)if