Offers in-depth discussions of test sequence generation and response data compression, including pseudorandom sequence generators; the mathematics of shift-register sequences and their potential for built-in testing. Also details random and memory testing and the problems of assessing the efficiency of ...
References (4) P.H. Bardell Calculating the effects of linear dependencies in m-sequences used as test stimuli P.H. Bardell et al. Built-In Test for VLSI: Pseudorandom Techniques (1987) There are more references available in the full text version of this article....
Savir: "built-in test for vlsi Login: a logic programming language with built-in inheritance Retarder film, polarizer with built-in retarder, and LCD device having the polarizer Linear objects: Logical processes with built-in inheritance
Table 7.Cost/benefit for BIT, viewed from VLSI perspective adapted from [35]. + cost increase, − cost reduction, +/− cost increase leading to saving. Empty CellDesign, test & dev.FabricationProduction testingMaintenance testingDiagnosis, repairService interruption ...
Testing requirements for the application of built-in self-test to fault tolerant circuits include: (1) detection of all single and multiple faults and (2) ... CE Stroud,JKT Jr - IEEE Vlsi Test Symposium 被引量: 18发表: 1998年 Logic Built In Self-Test Verification Statergy For SerDes PH...
机译:利用内置硬件对VLSI电路进行自我测试以自我检测 4. Manufacturing defects testing of a multi-chip-module using IEEE 1149.1 boundary scan test and embedded built-in test software [C] . Round, B.J. . 1993 机译:使用IEEE 1149.1边界扫描测试和嵌入式内置测试软件对多芯片模块进行制造缺陷测试 ...
We present a novel approach for built-in self test (BIST) for VLSI. Many conventional BIST schemes use signatures generated by a linear feedback shift register (LFSR) or a multiple input signature register (MISR) for determining whether the device under test is faulty or fault free. In the...
W. Maly and P. Nigh, “Built-in current testing for VLSI circuits,”Proc. of SRCTECHCONW Conf., Dallas, pp. 149–152, October 1988. Google Scholar W. Maly, “Design methodology for defect tolerant integrated circuits,”Proc. of CICC′88, Rochester, NY, pp. 27.5.1–27.5.4, May 198...
Click for automatic bibliography generation Assignee: VLSI Technology, Inc. Primary Class: 365/201 Other Classes: 365/189.07, 714/718 International Classes: G11C29/32;G11C29/44; (IPC1-7): G11C7/00 Field of Search: 371/21.1, 371/21.2, 365/201, 365/189.07 ...
A novel and pragmatic built-in self test technique provides cost-effective and thorough testing and diagnosis of content addressable memories (CAMS). The m... DK Bhaysar - IEEE Symposium on Vlsi Test 被引量: 15发表: 2005年 Built-In Self-Repair Techniques for Content Addressable Memories Lu,...