``` ERROR: [Opt 31-141] Invalid option [-vivado_version] ``` 5. ERROR: [Timing 38-35] The design failed to meet the timing requirements 在进行时序约束的时候,会出现这种错误。一般是由于时序较紧或者电路设计不合理导致。解决方法可以尝试优化时序约束,或者优化电路设计。 下面是一段伪代码: ```...
将AAA模块所有的信号连接好以后,在imp阶段就报错了,出现了Opt 31-67错误。[Opt 31-67] Problem: A LUT6 cell in the design is missing a connection on input pin I5, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due ...
这个原因主要是因为有一个引脚没有用到,解决方法。 1、打开Schematic。 2、根据提示的模块去找,比如说我的报错。 [Opt 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the de...
[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: Inst_XAUI_...
[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: Inst_XAUI_...
[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: sub_inst/...
70111 - Vivado 2017.3 - [Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I0 Description Migrating a Vivado design from 2017.2 to 2017.3 results in the following error: [Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on inpu...
[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: Inst_XAUI_...
ERROR: [Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: qdma...
71554 - Queue DMA subsystem for PCI Express (PCIe) (Vivado 2018.2) - [Opt 31-67] Problem: A LUT5 cell in the design is missing a connection on input pin I1 Description When the "AXI-lite slave interface" option is enabled, the following error is observed during the opt_design phase ...