Do you remember how to add the clock constraint and use the set_ Input_ Delay? LikeReply aestay (Member) Edited January 12, 2022 at 11:20 PM Check if the network you want to constrain survive synthesis or implementation, or it...
First, if "axi_clk" is a clock, it wouldn't really make sense to have a mark_debug on it. If the ILA is clocked by this clock, then you can't sample a clock with itself. Even if the ILA is clocked by a different (faster) clock, it is not...
I get this when building for Arty in Vivado v2019.2: CRITICAL WARNING: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_nets clk100]'. I didn't try to continue the build as it sounds too serious... Workaround I m...