这个错误的直接原因是Verilog不支持Data_i[i*8-1:i*8-8] 这种语法。如果把向量的位选取写成vect[ms...
我这段verilog为什么报错 i is not a constant？改成[(i*8-8)+:8]试试。不过还有很多其他问题，...
这个是用c语言写电路。那个for里面的i需要定义为genvar i；另外从你写的逻辑看，你是希望那个shift_reg不断的变化，但是你这么写的话。系统会认为是一个组合逻辑，所以会立刻计算出结果。你需要写成时续逻辑的电路，用always @（posedge clk）begin ...end 兄弟，北化的，师从何宾？
assign 不能放在if里，除非是generate if。如果用always，就不能用assign
//integer j; // Error:j is not a genvar;j is not a constantgenvarj;reg[data_width-1:0] in2_reg [0:depth-1];for(j=0;j<depth;j=j+1)begin:in2_loopalways@(posedgeclkornegedgerst_n)beginif(!rst_n) in2_reg[j] <=0;elsein2_reg[j] <= in2+j;endend ...
// It is wrong!! always@(posedge a or negedge a)begin b = not a; end 注意,只有时序逻辑才能用posedge和negedge关键字,虽然从代码事件解释来看上述两例好像功能相似,但是若出现沿事件关键字,则编译器会将程序块综合为时序逻辑,而这个世界上目前还没有既能够敏感一个信号上升沿又能够敏感这个信号下降沿的触...
-cll, --class-log-level<fullclassname:{error|warn|info|debug|trace}>...</fullclassname:{error|warn|info|debug|trace}> Set per-class logging verbosity --log-file Log to a file instead of STDOUT -lcn, --log-class-names Show class names and log level in logging output ...
26 Error: Can't resolve multiple constant drivers for net "datain_reg[22]" at shift_reg.vhd(19) 27 can't infer register for signal "num[0]" because signal does not hold its outside clock edge 28 Error: Can't elaborate top-level user hierarchy 29 Error: Can't resolve multiple const...
晕，你要给count赋值就要把count定义成reg型的，不能定义成integer（整数型），改成reg[31:0]count试试。把
Error (10742): Verilog HDL error at axis_thrower.sv(6): constant expression cannot contain a hierarchical identifier This should not be the case. With both Vivado and Verilator, the expression is allowed because their compilers deduce what is obviously constant at compile...