Learn about designing a multiplexer in verilog with example code, specifically a 4x1 or 4 to 1 mux
10`timescale1ns/1ns 11`include"mux_case.v" 12 13modulemux_case_tb; 14 15rega_i, b_i, c_i, d_i; 16reg[1:0] sel_i; 17wireq_o; 18 19initialbegin 20fork 21#0a_i=1'b0; 22b_i=1'b1; 23c_i=1'b0; 24d_i=1'b1; 25sel_i=2'b00; 26 27#10sel_i=2'b01; 28#20sel...
21 #0 a_i = 1'b0; 1. 22 b_i = 1'b1; 1. 23 c_i = 1'b0; 1. 24 d_i = 1'b1; 1. 25 sel_i = 2'b00; 1. 26 1. 27 #10 sel_i = 2'b01; 1. 28 #20 sel_i = 2'b10; 1. 29 #30 sel_i = 2'b11; 1. 30 #40 sel_i = 2'b00; 1. 31 #50 $finish; 1...