1. VCS的debug options有三個levels:-debug_all、-debug、-debug_pp。 2. -debug_pp是三種level當中,performance最好的。 3. -debug_pp是+memcbk, +vcsd, +vpi, -ucli 這些options的集合。
接着就是编写makefile 1all: clean com sim verdi23clean:4rm -rf56com:7vcs -full64 \8-f rtl.f -R +v2k \9-debug_access+all \10-timescale=1ns/100ps \11-fsdb +define+FSDB \12-l com.log1314sim:15./simv -l sim.log1617verdi:18verdi -f rtl.f -ssf *.fsdb -nologo & vcs -f...
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第⼀步，调⽤VCS⽣成simv。vcs -full64 -sverilog -debug_all -lca -kdb -timescale=1ns/1ps <verilog_file_name> 这⾥使⽤了-sverilog选项开启SystemVerilog⽀持。添加-kdb选项⽀持输出KDB格式的数据，⽤于与Verdi在交互模式交换数据，⽽KDB格式属于"Limited Customer Availability"特性，必须通过...
/bin/makeall:comp simcomp:vcs-full64 -timescale=1ns/1ps -V -R -sverilog \\ -debug_access+all +vc +v2k -kdb \\ -l vcs.log \\ -f dut.f +define+DUMP_FSDB=1 \\ -top testsim:./simv-l simv.logclean:rm-rf *~ core csrc simv* vc_hdrs.h ucli.key urg* *.log novas.* ...
SIM_OPTIONS := -timescale=1ns/1ns -fsdb -full64 -R +vc +v2k -sverilog -debug_all -P ${LD_LIBRARY_PATH}/novas.tab ${LD_LIBRARY_PATH}/pli.a -l vcs.log +incdir+${VSRC_DIR}/core/+${VSRC_DIR}/perips/ #To-ADD: to add the simulatoin tool options ...
-debug_access+all +vc +v2k -kdb \ -l vcs.log \ -f dut.f +define+DUMP_FSDB=1 \ -top test sim: ./simv -l simv.log clean: rm -rf *~ core csrc simv* vc_hdrs.h ucli.key urg* *.log novas.* *.fsdb* verdiLog 64* DVEfiles *.vpd ...
make all 自动完成clean、vcs、sim 6.模板 注意:命令的第二行必须Tab开头,使用\换行 .PHONE:com sim clean OUTPUT = adder_tb com: vcs -sverilog +v2k -timesscale=1ns/1ns \ -debug_all \ -o${OUTPUT}\ -l compile.log \ -f file.f ...
vcs ../de/top.v ../dv/tb_top.sv -timescale=1ns/1ps full64 -sverilog -debug_all |tee vcs.log下面是一些vcs指令常用的选项说明:VCS编译 vcs 启用vcs进行某些操作,必须放在命令的开头。 -full64 以64bit模式编译,输出文件是64bit。 -debug_access+all 用于仿真调试时的参数,all表示支持的功能...