A new SARADC has two low resolution SAR (Successive Approximation Register) ADCs coupled together by an amplifier to increase the overall resolution and enhance ADC conversion rate. The gain reduction of amplifier is corrected by shifting the digital binary output position. Two SAR ADC outputs are...
A 12 bit 160 MS/s two-step pipelined SAR ADC was fabricated in a 40 nm CMOS low-leakage digital process. A background bit-weight calibration exploiting the comparator resolving time information and the employment of a sub-binary DAC in the first SAR stage are two key techniques in this wo...
摘要: Low-noise ring amplifiers required for high-precision analog-digital converters (ADCs) greater than 16 b remain unexplored. This article demonstrates a two-step successive approxim... 查看全部>>关键词: 16-bit ADC analog-digital converter (ADC) low power ring amplifier (RAMP) two-step ...
This paper proposes a 13-bit parallel two-step single slope (TS-SS) ADC for high-speed CMOS image sensors. The ADC design method is based on the ideas of time sharing and time compression, moves the fine conversion time to the coarse conversion time period, and eliminates the traditional ...
By exploiting the respective advantages of the SAR and TDC architectures, the two-step ADC is realized without a high-gain amplifier for high linearity of a multiplying digital-to-analog converter. Thus, the proposed architecture can implement a low-power ADC without compromising operational speed....
A 14-bit two-step ADC is designed in 0.18 μm process and the equivalent power dissipation of the proposed ADC structure for one column is <20 μW. 机译:提出了一种用于红外焦平面阵列(IRFPA)的列级两步模数转换器(ADC)结构。第一步采用16列共享的6位闪存ADC来逐个完成16列的粗转换。由于交错...
A 12-Bit Two-Step SAR ADC with Linearized Open-Loop Amplifier In this paper, a new low power and configurable resolution two step flash ADC is proposed. Comparators of conventional flash ADC are replaced with CMOS inv... Y Cai 被引量: 0发表: 2017年 C-12-15 Study of a 6-bit 4.0-GH...
In this study, we develop a new kind of 6-bit flash ADC with a new two-step structure to greatly reduce the chip size. The first coarse 4-bit uses an array... SC Hsia,WC Lee - IEEE Design & Diagnostics of Electronic Circuits & Systems 被引量: 1发表: 2006年 A 2GSPS 6-bit Two...
A two-step, hybrid analog-to-digital converter (ADC) includes a Delta-Sigma ADC that employs chopping to resolve MSBs, a Nyquist ADC that employs correlated double sampling (CDS) to
The FoM is 127 fJ/conversion.关键词: CMOS integrated circuits delta-sigma modulation modulators operational amplifiers power consumption time-domain analysis CMOS DWA-embedded two-step time-domain quantizer SNDR bandwidth 8 MHz 会议名称: 2015 International Symposium on VLSI Design, Automation and Test ...