A shuffler receives the modulated digital input signal and the common mode control signal and generates a shuffled digital input signal. A digital to analog converter (DAC) has a plurality of tri-level unit DAC elements each receiving a corresponding portion of the shuffled digital input signal ...
The unit-capacitor array ADC has theoretically the lowest DAC power consumption. However, the digital circuit overhead is large. Two binary-weighted capacitor SAR ADCs were designed and implemented. A novel tri-level switching algorithm ... C Yuan 被引量: 1发表: 2014年 A Capacitor-Splitting Sw...
Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem...
Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem...
Conclusions: Postprandial elevation of TG and apoB-48 were independentof insulin secretion and insulin-resistance in patients with moderate orsevere hypertriglyceridemia.doi:10.1016/j.atherosclerosis.2017.06.685Daclat, RitaBittar, RandaSalem, Joe-Elie...
Decreasing the size of DAC capacitors is a solution to achieve high-speed and low-power successive-approximation register analog-to-digital converters (SAR... S Sarafi,AKB Aain,J Abbaszadeh - 《Microelectronics Journal》 被引量: 5发表: 2014年 Energy-efficient and area-efficient tri-level floati...