A Bi/Tri-level Self-Adaptive Two-Step DAC Switching Scheme for High-Power Efficiency SAR-Based ADCsSAR ADCTwo-stepReference voltage self-adaptive structureCapacitive switching schemeHigh energy-efficientA high energy-efficient and reference voltage self-adaptive switching scheme for a triple-capacitive ...
Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal charge redistribution DAC employs unit capacitance of 0.5 fF and ADC operates at nearly thermal noise limitation. To ...
A tri-level resistor DAC is also introduced as complementary to the new quantizer, enabling high DR while creating a dynamic power saving mechanism for the proposed design. Fabricated in 130nm CMOS, the ADC achieved peak Schreier FoM of 174.3dB with a high DR of 89dB over 0.4MHz BW, ...
A digital-to-analog converter (“DAC” or “D-to-A”) is a device that converts a digital (usually binary) code to an analog signal (e.g., a current, voltage, or electric charge). A switched resistor DAC is a type of DAC that contains a parallel network of DAC elements containing...
Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first
Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal charge redistribution DAC employs unit capacitance of 0.5 fF and ADC operates at nearly thermal noise limitation. To ...
Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem...
International Symposium on Circuits and SystemsKuan-Ting Lin; Kea-Tiong Tang, "A SAR ADC with energy-efficient DAC and tri-level switching scheme," Circuits and Systems (ISCAS), 2013 IEEE International Symposium on , vol., no., pp.2243,2246, 19-23 May 2013...
A digital to analog converter (DAC) has a plurality of tri-level unit DAC elements each receiving a corresponding portion of the shuffled digital input signal as a first input signal, and receiving second and third input signals. The tri-level unit DAC elements have first outputs coupled ...
Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been ...