PURPOSE:To form a high density semiconductor integrated circuit by forming the integrated circuit with one inverter, four P-channel MOS transistors(TRs) and four N-channel MOS TRs. CONSTITUTION:A control input terminal 11 is connected to each gate of P- channel MOS TRs 1, 2 and an N-...
A tri-state buffer circuit according to the present invention comprises a switching circuit (34) connected to an input terminal (IN), tri-state and inverted tri-state input terminals (T, T), and a first power supply terminal for generating first and second switching signals (A, B) which ...
A small sized tri-state buffer circuit that realizes a higher integration of semiconductor integrated circuits is provided. The tri-state buffer circuit includes an AND device that obtains a logical product of an input signal IN and a control signal, inverts the logical product and outputs the ...
TRISTATE BUFFER CIRCUIT 优质文献 相似文献Reduced power tristate driver circuit A tristate driver circuit is provided having a logic input signal, to produce a logic 1 output level or a logic 0 output level, and a float input signal, to produce float state operation. The circuit comprises a ...
Edge triggered tri-state output buffer A tri-state output buffer is provided which incorporates a dynamic depletion mode circuit. The tri-state buffer has an output driver circuit which includes a pull-up and a pull-down transistor device. Rapid switching of the pull-up trans... K Nishino,Y...
A first MOS (metal-oxide-semiconductor) NOR-gate device feeding a second MOS NOR-gate device feeding an MOS output load device is arranged to yield a three output level buffer circuit, that is, whose output to a common data bus line can be high ( 1 ), low ( 0 ), or of very high...
Tri state buffer circuit for dual power system A CMOS tri-state buffer circuit transfers digital signals between a first digital circuit system operating at 3.3 Volts and a second system operating at 5 Volts. The buffer circuit receives an active high enable signal and a data signal ... T ...
PURPOSE: To suppress current consumption even when both a 1st NMOS TR and a 2nd NMOS PTR are cut off when a common input terminal of the tri- state value input buffer circuit is open. ;CONSTITUTION: A potential at an intermediate point of PTRs 10,11 connected in series is set to 2.5V...
A current mirror transistor is included in a tristate logic buffer circuit, with its base and emitter respectively connected to the base and emitter of the phase splitter transistor and its collector connected to the voltage supply terminal. The emitter size of the current mirror transistor is a...
tristate device 【计】 三态器件 tristate output buffer 三态输出缓冲器 tristate bus line 三态总线 AND circuit 【计】 与电路 be the circuit of 绕...环行 not circuit 非电路 相似单词 tristate 三态; 三州间地区 circuit n. 1.环行,环行路线 2.电路,线路 3.巡回赛 4.赛车道 5.巡回...