A fourth input circuit formed of low level NAND gates is adapted for receiving a second input signal and has its outputs connected to the second node and the third node for turning off the lower output and upper output transistors so as to maintain the output circuit terminal in high ...
A two-phase non-overlapping clock generator (12) generating a sampling signal (20) utilizing a three transistor NAND gate (50). The NAND gate of the present invention eliminates one large PMOSFET (46), and has one NMOSFET (52) driven by the other phase and having its source grounded. ...
PROBLEM TO BE SOLVED: To provide a CMOS circuit for compatibly achieving a high-speed operation and low power consumption, particularly a 2-input CMOS-NAND gate circuit. SOLUTION: No matter which of the first gates of two vertically stacked 4-terminal double insulation gate field effect transis...
Abstract—There are several device challenges unique to the select gate transistor in 3D NAND memory cell. It requires low leakage current to prevent read and program disturb problems and it needs to provide enough current during read and erase operation. In this paper, we exam...
Overall, a percentage improvement of about half of the intrinsic figure can be expected at the chip level. Sign in to download full-size image Figure 20. Simulated 2-way NAND delays of bulk and SOI (body tied to the source) devices for Vdd=1.5 and 1.0 V versus load capacitance. The ...
A NOVEL SIDE-WALL TRANSFER-TRANSISTOR CELL ( SWATT CELL) FOR MULTI-LEVEL NAND EEPROMs A multi-level NAND Flash memory cell, using a new Side-WAll Transfer-Transistor(SWATT) structure, has been developed for a high performance and low bit cos... Seiichi Aritome,Yuji Takeuchi,Shinji Sato,....
When the cell must be erased, the word line is negatively biased in order to generate the appropriate voltage across the tunnel oxide; the selection line is positively biased, so that the bit line can set the drain voltage of the floating-gate device at the appropriate level. Due to the ...
we demonstrate that this single element enables one-to-one conversion of all three fundamental transistor circuit topologies and a wide range of classic electronic building blocks into the microfluidic domain including the amplifier, regulator, level shifter, NOT–AND (NAND) gate and set–reset (SR...
Mathematically,Δ0 = Vil-VolandΔ1 = Voh-Vih.Any noise that causes a noise margin to be overcome will result in a '0' being erroneously read as a '1' or vice versa. In other words, noise margin is a measure of the immunity of a gate from reading an input logic level incorrectly....
Novel NAND DRAM with Surrounding Gate Transistor (SGT)-Type Gain CellNovel NAND DRAM with Surrounding Gate Transistor (SGT)-Type Gain CellSurrounding gate transistor (SGT)SGT-type gain cellNAND DRAMLow-voltage operationA novel NAND DRAM with SGT-type gain cell is proposed. This SGT-type gain ...