An FPGA chip-based time-to-digital converter (TDC), comprising a pulse signal generator, a multi-tap signal delay chain, a trigger array, a connection network, a signal change edge searching and encoding circuit and a timestamp output circuit. The pulse signal generator is triggered by a ...
High-resolution Time-to-Digital converter (TDC) is one of the crucial blocks in Highenergy nuclear physics time of flight experiments. The contemporary time interval measurement techniques rely on employing methods like Time-to-Amplitude Conversion, Vernier method, Delay Locked Loops (DLL), Tapped ...
I am trying to implement a time-to-digital converter in Arria 10 FPGA, the schematic of which I have shown in the attached figure. I have many problems with this circuit because of its optimization by Quartus software. First of all, in HDL I described an adder to ...
I am trying to implement a time-to-digital converter in Arria 10 FPGA, the schematic of which I have shown in the attached figure. I have many problems with this circuit because of its optimization by Quartus software. First of all, in HDL I described an adder to ...
A 96-channel FPGA-based Time-to-Digital Converter (TDC) and fast trigger processor module with multi-hit capability and pipeline We describe an field-programmable gate arrays based (FPGA), 96-channel, Time-to-Digital converter (TDC) and trigger logic board intended for use with the C... Mi...
This paper proposes a bin-width tuning method for a field-programmable gate array (FPGA)-based delay line for a time-to-digital converter (TDC). Changing the hit transitions and sampling patterns of the carry chain considering delays of the sum and carry-out bins can improve the bin-width ...
Timing system was used to measure the time of flight(TOF) of laser pulse in light detection and ranging(LIDAR). Performance of a LIDAR system is directly influenced by the properties of the timing system. A time to digital converter(TDC) based on FPGA was designed for photon counting LIDAR...
The time-to-digital converter(TDC) is an equipment which aims to measure the accurate time of the edges of the input signal. Our work present an I/O Tile based multi-phase clock time-to-digital TDC, which is implemented in Field-Programmable-Gate-Array(FPGA). A hit signal is sampled by...
I am trying to implement a time-to-digital converter in Arria 10 FPGA, the schematic of which I have shown in the attached figure. I have many problems with this circuit because of its optimization by Quartus software. First of all, in HDL I described an adder to ...
I am trying to implement a time-to-digital converter in Arria 10 FPGA, the schematic of which I have shown in the attached figure. I have many problems with this circuit because of its optimization by Quartus software. First of all, in HDL I described an adder to...