#define TIM1_CCR3_ADDRESS 0x4001003C #define TIM1_DMAR_ADDRESS 0x4001004C /* TIM DMAR...
< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-tim...