R. Lin, Parallel VLSI shift switch logic devices", patent (pending) documentation (serial #: 09/022,248), 1998.R. Lin, Parallel VLSI Shift Switch Logic Devices, US Patent, Serial No. 09/022,248, 1999.R. Lin "Parallel VLSI Shift Switch Logic Devices", 1998
It was also predicted that NC-FETs may be plagued by hysteresis, if the capacitance matching process is inappropriately performed, which should be avoided in logic applications. Driven by the enthusiasm toward this novel “steep-slope” device, experimentalists have been indiscriminately trying to ...
These circuits are found to be suitable for VLSI implementation.doi:10.1155/2013/595296Srinivasulu AvireniRajesh MadugulaHindawiJournal of Engineering,2013,(2013-3-21)Avireni Srinivasulu and M. Rajesh, "ULPD and CPTL pull-up stages for Differential Cascode Voltage Switch Logic," Journal of ...
but as the number of switches grows, board space is not only occupied by the switches themselves but also by the logic control lines and associated passive components required for correct operation. Consequently
A new logic with shift switches incorporating novel parallel compressors and counters called C4 and (7,3) families. This shift switch logic deals with modulo arithmetic operations. It employs a type of special digital signals, called state signals (as a major addition to the binary signals), an...
The shift register ring design is advantageous from a VLSI standpoint because it uses short interconnections, low fan-out for the gates, and very few levels of logic, thus reducing the delay, and area; a critical requirement for a high bandwidth switch. Furthermore, the switch is designed ...
This crossbar design can be and has been implemented in various technologies, including specialized VLSI implementations with Domino logic. Sign in to download full-size image Figure 4-3. (a) Crossbar switch states. (b) Typical design of crossbar switch. The high cost of crossbar switches, ...
Computer Science Logic and Foundations of Programming Data availability The data that support the findings of this study are available from the corresponding author upon reasonable request. References Anjaneyulu O, Reddy CVK, 2023. A novel design of full adder cell for VLSI applications. Int J Ele...
Work is ongoing to implement this fabric in a standard-cell ASIC. A gate-level realization of the 2×4 SE building block has first been designed [8]. The logic design of the SE has been tested with VHDL. In addition to the master clock, the SE is timed by a Start pulse at each ...
IEEE Transactions on Acoustics, Speech, & Signal Processing-"Optimal Choice of Intermediate Latching to Maximize Throughput in VLSI Circuits", pp. 28-33. IEEE Journal of Solid-State Circuits, vol. SC-118-"NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures"-Goncalves & De Ma...