A cell switch architecture is proposed that provides resource allocation and buffer management features in the hardware. The cylinder switch system is specifically designed to take advantage of the properties of
A VLSI architecture for a high speed, non-blocking, cell switch is proposed. The architecture is particularly well suited for VLSI implementation, and is scalable to support many connections at high data rates. The switch employs a self-routing shift register ring design to transfer cells between...
The required switch cell for the switch matrix must be able to achieve two operational states using the “Turn” and “Thru” operations, as shown in Figure 17(b). The “Turn” operation implements a 90-degree rotation to the input signal, while the “Thru” operation provides a crossover...
cut-throughlatency,256-cellsharedbuffercontaining multiplelogicaloutputqueues,priorities,multicasting, andloadmonitoring.Thequeuemanagementblock ofATLASIisadualparallelpipelinethatmanagesthe multiplequeuesofreadycells,theper-flow-groupcred- its,andthecellsthatarewaitingforcredits.Allcells, ...
Weighted round-robin cell multiplexing in a general-purpose ATM switch chip The authors present the architecture of a general-purpose broadband-ISDN (B-ISDN) switch chip and, in particular, its novel feature: the weighted round-rob... Katevenis,M.,Sidiropoulos,... - 《Selected Areas in ...
A novel design of full adder cell for VLSI applications. Int J Electron, 110(4):670–685. https://doi.org/10.1080/00207217.2022.2059819 Article Google Scholar Cai YM, Huang R, 2014. Method for Inhibiting Programming Disturbance of Flash Memory. US Patent 20140017870. Cao ZZ, Shan YE, ...
An architecture for a Cell Switch Fabric (CSF) with a new bus assignment strategy is presented. The proposed architecture has a modular structure with a chip partitioning oriented to avoid the system from falling down totally, thus achieving expandability and increasing reusability. A discussion ...
A cell switch fabric chip is provided for use in different arrangements of fabric interfacing a cell body memory to N input ports and N output ports. Each port has a plurality of lines over which cons
Provided is a high-throughput large-capacity ATM switch in which variation in memory access time and data output delay time generated in the case where a DRAM is used as a cell buffer of the ATM switch is absorbed. To realize this, the ATM switch comprises a first memory using a DRAM fo...
Compensated current cell to scale switching glitches in digital to analog convertors. A compensated current cell is disclosed that includes first and second switching transistors configured to switch an input current between first and se... ミヒャエルジョセフマクゴワン 被引量: 0发表: 2018年 ...