#include "core_cm.h" // 包含Cortex-M内联函数的头文件 void DisableAllInterrupts(void) { // 禁用所有可屏蔽的中断 __disable_irq(); // 等同于 __set_PRIMASK(1) // 注意:通常不需要禁用FAULTMASK,因为它与错误处理相关 // __set_FAULTMASK(1); // 禁用所有硬故障中断,但一般不推荐 // 设置BAS...
cpsid i 关中断,但是不关硬fault 和NMI cpsid f 连硬fault也关了,只剩下NMI/*MCU上电初始化读取参数期间尝试关闭ALL中断,所以用的F,读取参数完成后再开启中断,进入主程序不用再用F中断*/ MDK的话可以直接书写(好像不对这是对应IAR): __disable_irq(); 相当于 CPSID I __enable_irq(); 相当于 CPSIE ...
其中/* Set HSION bit */可以看出系统初始化之后默认使用HSI作为系统时钟来源,因为不知道外部时钟是否准备好。 voidSystemInit(void){/* FPU settings ---*/#if(__FPU_PRESENT==1)&&(__FPU_USED==1)SCB->CPACR|=((3UL<<10*2)|(3UL<<11*2));/* set CP10 and CP11 Full Access */#endif/*...
cpsid f 连硬fault也关了,只剩下NMI/*MCU上电初始化读取参数期间尝试关闭ALL中断,所以用的F,读取参数完成后再开启中断,进入主程序不用再用F中断*/ MDK的话可以直接书写(好像不对这是对应IAR): __disable_irq(); 相当于 CPSID I __enable_irq(); 相当于 CPSIE I __disable_fiq(); 相当于 CPSID F _...
/* Disable all interrupts and clear pending bits */ RCC->CIR = 0x00FF0000; /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) ...
(uint32_t)0xFFFBFFFF;/* Disable all interrupts */RCC->CIR=0x00000000;#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)SystemInit_ExtMemCtl();#endif/* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM *//* Configure the Vector Table location add offset address ---*/#ifdef VECT_TAB...
/* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000; /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; #else /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000; #endif /* STM32F10X_CL */ ...
/* Disable all interrupts and clear pending bits */ RCC->CIR = 0x00FF0000; /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) ...
(uint32_t)0xFFFBFFFF;/* Disable all interrupts */RCC->CIR=0x00000000;#ifdefined(DATA_IN_ExtSRAM)||defined(DATA_IN_ExtSDRAM)SystemInit_ExtMemCtl();#endif/* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM *//* Configure the Vector Table location add offset address ---*/#ifdef VECT_TAB_SRAM ...
/* Disable all interrupts and clear pending bits */ RCC->CIR = 0x00FF0000; /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; #endif /* STM32F10X_CL */ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ ...