20 20 - Fix geometry instantiation in item-search-intersects.ipynb [#484](https://github.com/stac-utils/pystac-client/pull/484) 21 21 - Three tests that were false positives due to out-of-date cassettes [#491](https://github.com/stac-utils/pystac-client/pull/491) 22 + - Max it...
REGMAP_OFFSET.toSeq.sortBy(_._2):_*).map{case(k,v)=> (k, Integer.toHexString(v))}4 changes: 2 additions & 2 deletions 4 utils/srambist/src/bebe.rs Original file line numberDiff line numberDiff line change @@ -2,7 +2,7 @@ use crate::executor::Executor; use crate::pattern...
def apply(address: BigInt, tlbus: TLBusWrapper, tileNames: Seq[String], initResetHarts: Seq[Int])(implicit p: Parameters, v: ValName) = { val setter = LazyModule(new TileResetSetter(address, tlbus.beatBytes, tileNames, initResetHarts)) tlbus.toVariableWidthSlave(Some("tile-reset-sette...
54 + val packagePinsWithPackageIOs = Seq( 55 + ("G13", IOPin(harnessIO.bits.out.ready)), 56 + ("B11", IOPin(harnessIO.bits.out.valid)), 57 + ("A11", IOPin(harnessIO.bits.in.ready)), 58 + ("D12", IOPin(harnessIO.bits.in.bits, 0)), 59 + ("D13", clkIO...
def apply(th: HasHarnessInstantiators, chips: Seq[LazyModule])(implicit p: Parameters): Unit = { Seq.tabulate(chips.size, chips.size) { case (i, j) => if (i != j) { (chips(i), chips(j)) match { case (l0: HasIOBinders, l1: HasIOBinders) => p(MultiHarnessBinders(i, ...
lazy val commonSettings = Seq( organization := "edu.berkeley.cs", version := "1.6", scalaVersion := "2.13.10", assembly / test := {}, assembly / assemblyMergeStrategy := { _ match { case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case _ => MergeStrategy.first...
casePeripheryUARTKey=>Seq( UARTParams(address=0x54000000L, nTxEntries=256, nRxEntries=256, initBaudRate=baudrate)) /** * Config fragment for adding a GPIO peripheral device to the SoC * *@paramaddressthe address of the GPIO device
channelParamGen = (a, b) => UserChannelParams(Seq.fill(5) { UserVirtualChannelParams(4) }), routingRelation = NonblockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalLineRouting()), 5, 1)) )) ++0 comments on commit caff8a0 Please sign in to comment. ...
def trySuccessfulConf(requestedFreqs: Seq[Double], expected: Double): Unit = { val freqStr = requestedFreqs.mkString(", ") it should s"select a reference of ${expected} MHz for ${freqStr} MHz" in { it should s"select a reference of ${expected} MHz for ${freqStr} MHz" in { ...
(system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = GetSystemParameters(system) p(SerialTLKey).map({ sVal => val serialTLManagerParams = sVal.serialTLManagerParams.get val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.ge...