In: Proceedings of IEEE INFOCOM’96. Conference on Computer Communications, IEEE, vol. 1, pp 120–128 (1996) Bhagwan, R., Lin, B.: Fast and scalable priority queue architecture for high-speed network switches. In: Proceedings of the IEEE International Conference on Computer Communications (...
6.The processor as recited in claim 3 wherein a first store memory operation in the store queue is one of the plurality of sources. 7.The processor as recited in claim 3 wherein the load memory operation targets a plurality of registers, and wherein the atomicity size is a size of the...