testbench.v I wanted to learn verilog, so I created an own SPI implementation. Goals: Easy to read, easy to understand. Simple and flexible implementation. Features: SPI master / slave support all 4 modes (CPOL/CHPA) inverted data order support ...
🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc. - poucotm/Verilog-Gadget
All code is a Verilog behavior-level implementation that supports any FPGA platform. Except that the altpll block in fpga_top.v is an Altera Cyclone IV-only primitive that generates the 81.36MHz clock to drive the NFC controller. If you are not using Altera Cyclone IV, please use other IP...