verilog added config.tcl + pin.cfg for openlane flow Nov 14, 2021 xschem Succesfull post layout simulation of redrawn devices Oct 19, 2023 .DS_Store LVS succesfull for dac, comparator and latch in the new layout Oct 19, 2023 .gitignore Update include netlists Sep 20, 2021 .gitmodules ...
All the D-FFs are designed as C2MOS master-slave logic without asynchronous reset and are triggered with the master clock in order to have the D-FFs sampling at the same time. The Di signals are generated by D-GEN block using some Qi and Pi signals (with i=0..5) as inputs. The ...
The ADC was driven by asynchronous control logic, which was implemented using Verilog code and did not require a clock signal.N., MeghaShetty, PrajwalKudtarkar, Rahul R.Naik, Siddesh U.Abhilash, A. L.Journal of VLSI Circuits & Systems (JVCS)...
The ADC adopts a mixed digital–analog design scheme, in which the internal comparator, latch, DAC capacitor array, etc., are analog parts, and the rest of the SAR algorithms and calibration algorithms are all implemented in digital Verilog code, with a conversion accuracy of 0.8 mV and a ...
The ADC adopts a mixed digital–analog design scheme, in which the internal comparator, latch, DAC capacitor array, etc., are analog parts, and the rest of the SAR algorithms and calibration algorithms are all implemented in digital Verilog code, with a conversion accuracy of 0.8 mV and a ...