Breadcrumbs riscv-aia / test/ Directory actions More optionsLatest commit D3boker1 fix(tests): fix relative paths; fix ignore file c2f3d81· Jul 23, 2024 HistoryHistoryFolders and files Name Last commit message Last commit date parent directory .. aplic [4/4] project IPs uniformization May...
riscv_imsic_attr_ofshould shiftcpu_indexby 1 here to produce correct IMSIC attr. hypervisor: Create vcpu before initialize AIA Create a correspondingvcpuintest_create_aiato capture wrongly configured RISC-V IMSIC attr.
Provided with IOMMU and Advanced Interrupt Architecture (AIA) system IP SDK released with necessary ...
├── huancun # 香山 L2/L3 缓存子模块 ├── difftest # 香山协同仿真框架 └── read-to-run # 预建的仿真镜像文件 IDE 支持 bsp make bsp IDEA make idea 生成Verilog 运行make verilog以生成 verilog 代码。输出文件为build/XSTop.v。 更多信息详见Makefile。 仿真运行 环境搭建 设定环境变量NEMU_...
32位RISC-V处理器是基于RISC-V指令集的一种处理器架构。它采用了32位的寄存器长度,并支持RISC-V指令集中的R型、I型和J型指令格式。 该处理器具有简单、精简的指令集,包括基本的算术运算、逻辑运算和数据传输指令。它采用了固定长度的指令格式,使得指令解码和执行过程更为高效。 该处理器的寄存器组包括32个32位...
支持Sstc、Ssovfpmf 和 Smaia 等新扩展 修复了旧版实现的一系列 Bug Bug 修复 修复vsstatus.vs 检测的 bug(#3253) 修复vfredosum 指令的 uop num(#3230) 时序优化 优化og0 cancel 信号时序(#3235) decode 的 isComplex 移除 uopNum =/= 1.U 的条件判断 访存与缓存 CHI 总线 CHI-L3 完成剩余模块设计...
test/aia_test_cert.pem /usr/share/cargo/registry/openssl-0.10.64/test/alt_name_cert.pem /usr/share/cargo/registry/openssl-0.10.64/test/authority_key_identifier.pem /usr/share/cargo/registry/openssl-0.10.64/test/ca.crt /usr/share/cargo/registry/openssl-0.10.64/test/cert.pem /usr/share/...
In addition to the above standards, X100 also supports RISC-V bit operation instruction standard B, DEBUG standard, advanced interrupt standard AIA and several other functions.Innovation in MicroarchitectureX100’s microarchitecture has the advantages of both high performance and high energy efficiency. ...
RISC-V CPU core X100, AIA and APLIC supporting interrupt virtualization, IOMMU supporting memory virtualization, IOPMP supporting security functions, LPC and eSPI supporting communication with mainstream BMCs, etc. The 64-bit server-grade RISC-V CPU core X100 delivers a single-core performance of >...
Add definition of low-priority and high-priority RAS event from AIA (r… Feb 27, 2024 parse.py Merge pull requestriscv#167from Lucas-Wye/master May 2, 2023 requirements.txt adding python dependencies to requirements.txt May 2, 2022