介绍进迭时空的X100芯片上的IO虚拟化。详细说明了RISC-V周边IP—IOMMU、AIA、IOPMP模块。 利用人工智能大模型优化 RISC-V 编译器的性能 介绍了对编译器利用大模型优化的探索。包括大模型选择优化参数、优化执行顺序和直接利用大模型优化代码、生成自定义指令。 8月23日上午A会场 OpenJDK on RISC-V (PLCT) 介绍...
Add definition of low-priority and high-priority RAS event from AIA (r… Feb 27, 2024 parse.py Merge pull requestriscv#167from Lucas-Wye/master May 2, 2023 requirements.txt adding python dependencies to requirements.txt May 2, 2022
riscv_imsic_attr_ofshould shiftcpu_indexby 1 here to produce correct IMSIC attr. hypervisor: Create vcpu before initialize AIA Create a correspondingvcpuintest_create_aiato capture wrongly configured RISC-V IMSIC attr.
支持Sstc、Ssovfpmf 和 Smaia 等新扩展 修复了旧版实现的一系列 Bug Bug 修复 修复vsstatus.vs 检测的 bug(#3253) 修复vfredosum 指令的 uop num(#3230) 时序优化 优化og0 cancel 信号时序(#3235) decode 的 isComplex 移除 uopNum =/= 1.U 的条件判断 访存与缓存 CHI 总线 CHI-L3 完成剩余模块设计...
Revert "feat(AIA): integrate ChiselAIA (#4378)" (#4429) 8小时前 Makefile.test test: add example of chiseltest's unit-test and generating verilog for… 2年前 README.md docs(README): update copyright and license 2个月前 build.sbt Add sbt build support (#857) 4年前 ...
Provided with IOMMU and Advanced Interrupt Architecture (AIA) system IP SDK released with necessary ...
test/aia_test_cert.pem /usr/share/cargo/registry/openssl-0.10.64/test/alt_name_cert.pem /usr/share/cargo/registry/openssl-0.10.64/test/authority_key_identifier.pem /usr/share/cargo/registry/openssl-0.10.64/test/ca.crt /usr/share/cargo/registry/openssl-0.10.64/test/cert.pem /usr/share/...
In addition to the above standards, X100 also supports RISC-V bit operation instruction standard B, DEBUG standard, advanced interrupt standard AIA and several other functions.Innovation in MicroarchitectureX100’s microarchitecture has the advantages of both high performance and high energy efficiency. ...
RISC-V CPU core X100, AIA and APLIC supporting interrupt virtualization, IOMMU supporting memory virtualization, IOPMP supporting security functions, LPC and eSPI supporting communication with mainstream BMCs, etc. The 64-bit server-grade RISC-V CPU core X100 delivers a single-core performance of >...
#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA @@ -70,12 +74,15 @@ unsigned long riscv_get_elf_hwcap(void); struct riscv_isa_ext_data { /* Name of the extension displayed to userspace via /proc/cpuinfo */ char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; /* The logical ISA e...