riscv_imsic_attr_ofshould shiftcpu_indexby 1 here to produce correct IMSIC attr. hypervisor: Create vcpu before initialize AIA Create a correspondingvcpuintest_create_aiato capture wrongly configured RISC-V IMSIC attr.
ChiselAIA是RISC-V高级中断架构(Advanced Interrupt Architecture, AIA)的开源Chisel实现。现有的开源AIA实现主要是用Verilog编写的相关工作。 ChiselAIA旨在将Chisel敏捷开发的方法应用于AIA的实现。 ChiselAIA is an open-sourced Chisel implementation of the RISC-V Advanced Interrupt Architecture (AIA). Existing open...
支持Sstc、Ssovfpmf 和 Smaia 等新扩展 修复了旧版实现的一系列 Bug Bug 修复 修复vsstatus.vs 检测的 bug(#3253) 修复vfredosum 指令的 uop num(#3230) 时序优化 优化og0 cancel 信号时序(#3235) decode 的 isComplex 移除 uopNum =/= 1.U 的条件判断 访存与缓存 CHI 总线 CHI-L3 完成剩余模块设计...
feat(AIA): integrate ChiselAIA (#4378) 4天前 Makefile.test test: add example of chiseltest's unit-test and generating verilog for… 2年前 README.md docs(README): update copyright and license 2个月前 build.sbt Add sbt build support (#857) 4年前 build.sc feat(AIA)...
Provided with IOMMU and Advanced Interrupt Architecture (AIA) system IP SDK released with necessary ...
In addition to the above standards, X100 also supports RISC-V bit operation instruction standard B, DEBUG standard, advanced interrupt standard AIA and several other functions.Innovation in MicroarchitectureX100’s microarchitecture has the advantages of both high performance and high energy efficiency. ...
test/aia_test_cert.pem /usr/share/cargo/registry/openssl-0.10.64/test/alt_name_cert.pem /usr/share/cargo/registry/openssl-0.10.64/test/authority_key_identifier.pem /usr/share/cargo/registry/openssl-0.10.64/test/ca.crt /usr/share/cargo/registry/openssl-0.10.64/test/cert.pem /usr/share/...
-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xc...
RISC-V CPU core X100, AIA and APLIC supporting interrupt virtualization, IOMMU supporting memory virtualization, IOPMP supporting security functions, LPC and eSPI supporting communication with mainstream BMCs, etc. The 64-bit server-grade RISC-V CPU core X100 delivers a single-core performance of >...
- A Linux-based setup using the [RISC-V IOMMU Driver](https://github.com/tjeznach/linux/tree/tjeznach/riscv-iommu-aia) developed by the RISC-V IOMMU Task Group. - A virtualization-based software stack using [Bao hypervisor](https://github.com/bao-project/bao-hypervisor) with support ...