isa目录 benchmarks目录 env目录 debug目录 tool目录 既然是开源测试集,那就先贴上仓库链接,如下 GitHub - riscv-software-src/riscv-testsgithub.com/riscv-software-src/riscv-tests 从验证角度看riscv-tests 从验证的角度看,riscv-tests仅仅作为前期指令通路的定向测试。在core开发初期稳定后,如果其能够稳...
riscv-tests目录放的是isa、debug、mt和benchmarks的测试文件、底层相关驱动、及其编译的文件，用于测试...
2 changes: 2 additions & 0 deletions 2 apps/riscv-tests/isa/rv64uv/Makefrag Original file line numberDiff line numberDiff line change @@ -113,10 +113,12 @@ rv64uv_sc_tests = vadd \ vl1r \ vle1 \ vls \ vluxei \ vs \ vs1r \ vse1 \ vss \ vsuxei \ vsetivli #rv64...
The Linux kernel is seemingly infinitely configurable. However, with the current development status, there aren't that many devices or options to tweak. However, start with a default configuration that should work out-of-the-box with the ISA simulator. ...
RISC-V is an open-source standard ISA with exceptional modularity and extensibility. Anyone can build an implementation and there are no license fees, except for commercial use of the trademarks. … Implementers are free to add custom extensions to boost capabilities and performance, while at the...
Test programs for therv32u*andrv64u*TVMs can contain all instructions from the respective base user-level ISA (RV32 or RV64), except for those with the SYSTEM major opcode (syscall, break, rdcycle, rdtime, rdinstret). All user registers (pc, x0-x31, f0-f31, fsr) can be accesse...
However, start with a default configuration that should work out-of-the-box with the ISA simulator.$ make ARCH=riscv defconfig If you want to edit the configuration, you can use a text-based GUI (ncurses) to edit the configuration:O$ make ARCH=riscv menuconfig ...
output/%.run: $(srcDir)/riscv-tests/isa/% emulator ./emulator +max-cycles=$(asm_test_timeout) +loadmem=$< none $(disasm_exe) /dev/null output/%.out: output/%.hex emulator output/%.out: $(srcDir)/riscv-tests/isa/% emulator -./emulator +max-cycles=$(asm_test_timeout) +load...
10 changes: 10 additions & 0 deletions 10 isa/rv32si/Makefrag Original file line numberDiff line numberDiff line change @@ -5,6 +5,16 @@ rv32si_sc_tests = \ csr \ shamt \ ma_fetch \ fa_fetch_zscale_8192 \ illegal \ privileged \ scall \ sbreak \ ma_addr \ fa_addr_z...
Spike, a RISC-V ISA Simulator. Contribute to Silicon-wzh/riscv-isa-sim development by creating an account on GitHub.