dcache.ciall 即flush L1 dcache，类似标准的cbo指令，但是不需要指定地址可以清空整个dcache。即用于ca...
Let's add macros for cbo inline asms in include/zephyr/arch/riscv/csr.h 😄 1 Collaborator Author kevinwang821020 Dec 1, 2023 OK, I will do the modification for your recommendation. Thanks a lot. arch/riscv/core/cache.c Outdated return 0; } #endif Member fkokosinski Nov ...
RISC-Vis progressing nicely with the following changelog. Support for cbo.zero in userspace Support for CBOs on ACPI-based systems A handful of improvements for the T-Head cache flushing ops Support for software shadow call stacks Various cleanups and fixes Allwinner RISC-V DT cleanups Added new...
64 ok 2 cbo.zero ok 3 cbo.zero check # Totals: pass:3 fail:0 xfail:0 xpass:0 skip:0 error:0 * b4-shazam-merge: riscv: Save/restore envcfg CSR during CPU suspend riscv: Add a custom ISA extension for the [ms]envcfg CSR riscv: Fix enabling cbo.zero when running in M-mode...
Mergedlast week was support for cbo.zero in user-space, support for CBOs on ACPI-based RISC-V systems, support for software shadow call stacks, improvements for the T-Head cache flushing operations, and other clean-ups and fixes. This software-basedShadow Call Stacksupport for RISC-V relies...
Support for cbo.zero in userspace Support for CBOs on ACPI-based systems A handful of improvements for the T-Head cache flushing ops Support for software shadow call stacks Various cleanups and fixes Allwinner RISC-V DT cleanups Added new ISA property and PMU node to Allwinner D1 ...
Support for cbo.zero in userspace Support for CBOs on ACPI-based systems A handful of improvements for the T-Head cache flushing ops Support for software shadow call stacks Various cleanups and fixes Allwinner RISC-V DT cleanups Added new ISA property and PMU node to Allwinner D1 ...
Accessing the same location using different cacheability attributes may cause loss of coherence. Executing the following sequence between such accesses prevents both loss of coherence and loss of memory ordering:fence iorw, iorw, followed bycbo.flushto an address of that location, followed by afenc...
if(cboz_block_size) riscv_cboz_block_size=cboz_block_size; } #ifdefCONFIG_SMP staticvoidset_icache_stale_mask(void) { cpumask_t*mask; boolstale_cpu; /* * Mark every other hart's icache as needing a flush for * this MM. Maintain the previous value of the current ...
Release riscv-isa-release-62cb1e7-2024-09-27Latest This release was created by: aswaterman Release of RISC-V ISA, built from commit62cb1e7, is now available. What's Changed Zicfiss clarifications: CBO and PM by@ved-rivosin#1657