In SDK v17.1.0, In QSPI init, I see all the pins are configured as Input pins during nrfx_qspi_init. Isn't this wrong? Shouldn't we set the SCLK, CSN, MOSI pins as O/P pins? and why Input buffer disconnected for input pins? /** * @brief Macro for i...
Solved: if u-boot configures QSPI for AHB reads, the M4 must clear the QUADSPI_BFGENCR register during its init to bring it back to a well known
Support GD28LQ128 QSPI flash Browse files Signed-off-by: MichaelZhuxx <michael.zhu@starfivetech.com>starfive MichaelZhuxx committed Nov 2, 2021 1 parent 0084526 commit d086aee Showing 1 changed file with 3 additions and 2 deletions. Whitespace Ignore whitespace Split Unified 5 changes: 3...
if u-boot configures QSPI for AHB reads, the M4 must clear theQUADSPI_BFGENCR register during its init to bring it back to a wellknown state.void QSPI_SoftwareReset(QuadSPI_Type *base) { uint32_t i = 0; /* Reset AHB domain and buffer domian */...