A method of delaying successive first and second input signals by first and second different selectable time periods using a programmable delay line comprising a sequence of delay elements, each introducing a delay, the method comprising the steps of: providing a control signal to each delay ...
11. The digital logic functionality is to generate the control bits to the core DCC, on the right side of Fig. 12. The MSB of the input 4- bits, is a “decision bit” to correct the duty cycle on positive side (more than 50%) or negative side (less than 50%). Other 3-bits ...
The advantage of this arrangement is that the negative feedback eliminates any effects caused by device error (deviation between actual delay and programmed delay). Figure 6. Ultrasonic rangefinder application. A digital ultrasonic rangefinder is shown to illustrate the use of the DS1020/DS1021 in ...
Programmable time delay circuit for digital logic circuits MC Swapp 被引量: 12发表: 1991年 Programmable Delay Circuit H Jan 被引量: 0发表: 2011年 Programmable delay circuit Programmable delay with: (A) an oscillator (4) responsive to an input signal (PT) and is used for generating ...
FPGA has a programmable delay digital unit, which is widely used in communication systems and various electronic devices, such as synchronous communication systems, time numerical systems, etc. The main design methods include CNC delay line method, memory method, counter method Etc., where the memor...
An all-digital self-calibrated delay-line based temperature sensor for VLSI thermal sensing and management This paper presents a low power self-calibrated delay-line based temperature sensor intended for Very Large Scale Integration (VLSI) thermal management app... S Xie,WT Ng - 《Integration the...
A field-programmable gate array (FPGA) is an integrated circuit that can be configured to implement different digital logic functions. Conventionally, FPGA is used as an emulation platform for early-stage validation of application-specific integrated circuit (ASIC). It is now extensively used for HP...
A delay locked loop (DLL) may be implemented using either digital or analog circuits. A typical conventional digital implementation includes a delay line formed using a long series chain of inverters. The delay line may be tapped at many nodes along the chain such as between every other inverte...
A multi channel digital delay/pulse generator for time of flight (TOF) mass spectrometer was designed. The application of complex programmable logic device (CPLD) and digital programmable delay line AD9501 in the system is described. The... G Hui,W Chen,J Wang,... - 《Analytical Instrumentat...
Consequently, the SPLD can be used to integrate the functions of a number of discrete digital ICs into a single device and the CPLD can be used to integrate the functions of a number of SPLDs into a single device. The CPLD architecture is based on a small number of logic blocks and a...