PURPOSE:To effectively utilize a memory capacity and to reduce the price of a whole circuit by providing a digital line memory to delay an input video signal by two lines and output it and a digital line memory to have a capacity to be able to store the video signal equivalent to one ...
美 英 un.数据延时线;数字式延迟线 英汉 un. 1. 数据延时线 2. 数字式延迟线 例句
5) Digital delay line 数字延迟线 1. A new time-digital convert circuit based on digital delay line; 一种基于数字延迟线的新型时间数码变换电路 2. By combining the beamformer structure of a FIR filter fan and digital delay lines, the order of a FIR filter fan is reduced. ...
A digital delay cell and a delay line circuit having the same are provided to reduce power consumption and obtain output signals of various phases by improving a duty characteristic and an output signal characteristic of the delay cell and the delay line circuit. A delay line circuit having a ...
A digital delay circuit and a digital PLL circuit achieve reduction in size and power consumption. Each of a first delay line (301) and a second delay line (302) includes a plurality of delay elements. A control circuit (200) selects the delay element(s) included in a delay line (300...
Two-channel high-voltage trigger generator using artificial transmission line as time-delay circuit; 将多路高电压触发器的运行模式从"先延时后触发"改变为"先触发后延时",并用人工传输线代替集成电路芯片构成时延电路,这大大提高了多路高电压触发器的抗电磁干扰能力。5...
6) Digital delay line 数字延迟线 1. A new time-digital convert circuit based on digital delay line; 一种基于数字延迟线的新型时间数码变换电路 2. By combining the beamformer structure of a FIR filter fan and digital delay lines, the order of a FIR filter fan is reduced. ...
DIGITAL DELAY CIRCUIT
A phase and frequency detector coupled to the registered outputs of the tapped digital delay line determines the phase and frequency relationship between the recovered clock (DCO clock) and the transmit clock. A filter and control circuit then uses this information to generate a "servo" control ...
The first method constitutes a clock shaper circuit that produces an output clock that has a 50% duty cycle regardless of the duty cycle of the input reference clock. The second technique generates an internal clock that is an N/2 multiple of the frequency of the input clock, where N is ...