As mentioned, unique is only for case statements since more than one condition can match with a Verilog case statement. if-else implies a priority encoder so that is not what you want. You should be using a case statement and if there is the possibility of more ...
Firstly, by adding the SystemVeriloguniquekeyword, the designer asserts that only onecase itemcan match at a time. If more than one bit ofirqis set in simulation, the simulator will generate a warning, flagging that the assumption ofirqbeing one-hot has been violated. Secondly, to synthesis...
The reasons cited most often by engineers for using full_case parallel_case were: • full_case parallel_case makes my designs smaller and faster. • full_case removes latches from my designs. • parallel_case removes large, slow priority encoders from my designs. The above reasons were...