This example will simulate like a priority encoder but will infer non-priority encoder logic when synthesized, as shown in Figure 11. SNUG2005 Israel Rev 1.0 11 SystemVerilog's priority & unique - A Solution to Verilog's "full_case" & "parallel_case" Evil Twins! module intctl1b (output...
priority encoder further utilizes a dynamic circuit layout so that chip area is conserved while maintaining the requirements of a high speed CAM. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, ...