ML605:virtex6 DDR3调试 phy_init_done无法拉高问题 技术标签:FPGA 文章目录 其他一些问题 关于选错了器件型号 如何看仿真图 关于仿真环境 关于仿真环境(补充) 直接说结论吧。vivado不支持6系列FPGA,以及ise生成IP的RTL文件。仿真也不行! 在使用IP生成MIG后,我将MIG对应的RTL、sim文件放到vivado里仿真了。我以为...
首先你要确认DDR2 IP 核上的所有信号是否都用到了，我当时有过因为DM引脚没有分配造成初始化无法完成。然后就是确认硬件没有问题，例如DDR2芯片是好的，电压是正常的等，我当时因为DDR2 芯片有过问题，一直不能初始化完成，而且个人觉得现在DDR2芯片很多有问题。至于你里面问的三个问题，第一个问题，...
Devices always starting and working normal, but in a one moment local_init_done going LOW and after not going HIGH never. Only after global reset alt_mem_phy DDR2 controller release local_init_done ('1'). Device can working all day, but can work only few...
Devices always starting and working normal, but in a one moment local_init_done going LOW and after not going HIGH never. Only after global reset alt_mem_phy DDR2 controller release local_init_done ('1'). Device can working all day, but can work only few minutes. Th...