Describe some of the common source - different embodiments cascade phase-locked loop structure. 在一个实施例中,设备可以包括具有多个部分共源-共栅电路(206,914,924)的锁相环电路(1000). In one embodiment, the apparatus may comprise a plurality of portions having a common source - cascode circuit (...
[1] Liu H L, Shirane A, Okada K, et al. A 265-μW fractional-N digital PLL with seamless automatic switching sub-sampling/sampling feedback path and duty-cycled frequency-locked loop in 65-nm CMOS. IEEE J Solid-State Circuits, 2019, 54, 3478 [2] Fan Y P, Xiang B, Zhang D, e...
[4] Su, Pin-En, and Sudhakar Pamarti. "Fractional-$ N $ Phase-LockedLoop-Based Frequency Synthesis: A Tutorial." IEEE Transactions on Circuits and Systems II: Express Briefs 56.12 (2009): 881-885. [5] B. Razavi, Design of CMOS phase-locked loops: from circuit level to architecture le...
Phase-locked loop-based clock generation is popular in data communication and radar applications, as it generates highly stable, low noise-affected, high-frequency clocks up to tens of gigahertz. In wireless communication, phase-locked loops (PLL) are imperative blocks that enable clock recovery,...
Phase-locked loop (PLL) circuits exist in a wide variety of high frequency applications, from simple clock clean-up circuits, to local oscillators (LOs) for high performance radio communication links, and ultrafast switching frequency synthesizers in vector network analyzers (VNA). This article expla...
anormalized frequency of DDFS. They can be dominant if they [translate] a(DDFS)-driven phase-locked loop (PLL) architecture, which [translate] 英语翻译 日语翻译 韩语翻译 德语翻译 法语翻译 俄语翻译 阿拉伯语翻译 西班牙语翻译 葡萄牙语翻译 意大利语翻译 荷兰语翻译 瑞典语翻译 希腊语翻译 51La ...
United States Patent US7936223 Note: If you have problems viewing the PDF, please make sure you have the latest version ofAdobe Acrobat. Back to full text
The present invention relates to phase-lock loop circuits. More particularly, the present invention relates to a multiple voltage controlled oscillator phase-locked loop architecture. BACKGROUND Phase-lock loops (PLL) may include a phase-frequency detector (PFD) that provides control signals indicative...
It offers a very fast capture, output phase jitter small and stable steady state phase-locked loop (PLL). 通常,锁相环被用于将所说的锁相环的输出信号与输入参考信号同步. Typically, the phase locked loop of said phase locked loop is used to output the reference signal synchronized with the ...
We propose a novel architecture of an oscillatory neural network that consists of phase-locked loop (PLL) circuits. It stores and retrieves complex oscilla... FC Hoppensteadt,EM Izhikevich - 《IEEE Trans Neural Netw》 被引量: 291发表: 2000年 PHASE-LOCKED LOOP DELAY LINE A circuit for prov...