1,176 Views When implementing PCIe using Qsys on a Cyclone IV GX, should there be a PLL between the refclk pin (100 MHz from connector) and the PCIe IP block? Reference designs do not seem to have one. When I compile without a PLL, I get a critical warning: ...
create_clock -name {pcie_refclk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {pcie_refclk}] set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to pcie_refclk Status: FAILSeverity: MediumNumber of violations: 8Rule Parameters: max_violations = 5000maximum_pulse_wi...
The IMAX8 PCIE_REFCLK100M can use as a resource for output?or need external clock input. Thank you0 Kudos Reply All forum topics Previous Topic Next Topic 1 Reply 02-27-2020 04:35 PM 701 Views igorpadykov NXP Employee Hi >The IMAX8 PCIE_REFCLK100M can use as a resource ...