网络通道晶体管逻辑;传输逻辑;传输管电路 网络释义
Dynamic and Pass-Transistor LogicProf. Vojin G. OklobdzijaReferences (used for creation of the presentation material):1.Masaki, “Deep-Submicron CMOS Warms Up to High-Speed Logic”, IEEE Circuits and Devices Magazine, November 1992.2.Krambeck, C.M. Lee, H.S. Law, “High-Speed Compact Circ...
This paper presents a comprehensive analysis of the effects of increased temperature on maximum power-efficiency (powerd-delay-product) of pass-transistor networks operating at low supply voltages using deep-submicron CMOS technology. Numerous gate functions, such as OR, NOR, AND, NAND, XOR and ...
in the corresponding conventional CMOS circuit27,28. This savings in the use of transistors in ICs not only leads to higher efficiency per transistor and lower power dissipation, but also to higher speed due to the shorter signal path. Simultaneously, the performance of CMOS-based PTL circuits ...
aPseudo-NMOS, static complementary CMOS, pass-transistor logic, differential logic: logic gate design and parameters, SPICE simulation 冒充NMOS,静态补全CMOS,通过晶体管逻辑,有差别的逻辑: 逻辑门设计和参量,香料模仿 [translate] 英语翻译 日语翻译 韩语翻译 德语翻译 法语翻译 俄语翻译 阿拉伯语翻译 西班牙语...
Differential and pass-transistor CMOS logic for high performance systems This paper presents a review of differential and pass-transistor logic used in today's high performance systems. Various circuit and logic design styles us... VG Oklobdzija - 《Microelectronics Journal》 被引量: 33发表: 1998...
Unlike a previous system for pass-transistor logic, PTM integrates both synthesis and logic optimisation in one step and can be used for large logic functions. Results from using PTM on a large set of benchmarks are analysed using the MCNC CMOS cell library and are found to be promising. ...
vlsi circuit design 04 pass transistor logic VLSICircuitsDesignPassTransistorLogic WangYong-sheng yswang@hit.edu.cn HarbinInstituteofTechnologyMicroelectronicsCenter Review:StaticComplementaryCMOSHITMicroelectronics Highnoisemargins VOHandVOLareatVDDandGND,respectivelyVDD Lowoutputimpedance,high In1 inputimpedance ...
Here we show that both drawbacks can be eliminated in CNT-based PTL cir- cuits via threshold voltage engineering and combining PTL circuits with CMOS inverters. Basic logic gates such as OR and AND, as well as the more complex full adder, multiplexer (MUX) and demulti- plexer (DEMUX) ...
LOW POWER, LOW LATENCY, HIGH THROUGHPUT 16-BIT CSA ADDER USING NONCLOCKED PASS-TRANSISTOR LOGIC As the CMOS technology continues to scale to achieve higher performance, power dissipation and robustness to leakage and, process variations are becoming m... C Senthilpari,K Diwakar,AK Singh - 《Jou...