SciaRegs.SCIFFRX.bit.RXFFOVRCLR = 1; // Clear Overflow flag SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; // Clear Interrupt flag PieCtrlRegs.PIEACK.bit.ACK9 = 1; } 实际运行时,发现SciaRegs.SCIRXBUF中,SCIFFPE=1(parity error),SCIFFFE=1(frame error) 但是检查了设...
parity error 美 英 un.奇偶校验误差;校验错误;奇偶校验差错 网络奇偶错误;奇偶校验错误;奇偶校验位错误 英汉 网络释义 un. 1. 奇偶校验误差 2. 校验错误 3. 奇偶校验差错 例句
memory parity interrupt存储奇偶中断,存储器奇偶中断 drun parity error【电】 磁鼓配类误差 unrecoverable parity error【计】 不可恢复奇偶性错误 address parity error地址奇偶错 drum parity error磁鼓奇偶错 相似单词 Parityn. 奇偶校验 n. 同等,同格,同位,平价 ...
The address translation unit includes a parity checker configured to verify the parity of the real address generated by the TLB and to signal the load store unit when the real address contains a parity error. The load store unit is configured to initiate a TLB parity error interrupt routine ...
Interrupt exception, CPU signal 20, PC = 0x[dec] Explanation This is the result of a single-bit parity error in the CPU L2 cache (SRAM) used by the Cisco Catalyst 6700 Series modules. Recommendation Monitor the system regularly for reocurrence. If no further events are observed, it is ...
parity check interrupt 奇偶检验中断 memory parity error 存储器奇偶错 memory parity generator 存储器奇偶发生器 No Parity 无同位数据传输无侦错位。 no parity 【计】 无奇偶校验 to interrupt 干扰;断续 相似单词 Parity n. 奇偶校验 n. 同等,同格,同位,平价 parity n. 1.同等,相等,对等 2.【...
2) storage parity interrupt 存储器奇偶校验中断3) Parity Check 奇偶校验 1. Nicety and continuity of data transfer are important performance indexes in serial communication system,usually certain error-tolerant technology is adopted,widely used are parity check,CRC,hamming code check and so on,but...
PURPOSE:To immediately stop the transmission of a parity error output by detecting clock interrupt through three consecutive bits of a clock at a receiver side reaching the same level as the sender side clock so as to reset 2-stage of FFs of an inhibit circuit. CONSTITUTION:A clock interrupt...
Board Parity Error; Memory Parity Interrupt; Jotting down the PC function that caused the error message and the address associated with the error; Clues about how to avoid recurrent parity errors; Use of a chip puller to remove memory chips one at a time....
专利名称：PARITY ERROR GENERATION INHIBIT CIRCUIT 发明人：KAWABE KAZUNORI,SAKAI TOSHIYUKI 申请号：JP1469890 申请日：19900124 公开号：JPH03219735A 公开日：19910927 专利内容由知识产权出版社提供 摘要：PURPOSE:To immediately stop the transmission of a parity error output by detecting clock interrupt through ...