For my project I have high speed pulses coming from an APD that is to processed by the FPGA, but the Nexys A7 board does not have any obvious pins to accept the fast pulses, since there are no pins with the impedance matching. So is there a way around th
I understand that, the only reason I mentioned LVDS is just because that is what the Xilinx datasheet refers to when discussing performance characteristics. According the the datasheet, the -1 speed grade (as is used on the Nexys video I believe) has a max transmitter / receiver speed of ...