Here we report a four-megabit nvCIM macro that combines memory cells with peripheral circuitry and is based on 22-nm-foundry binary resistive random-access memory devices and complementary metal–oxide–semicon
4脳4 memory architecture along with peripheral circuitry such as Asym7T SRAM cells array, decoder and sense amplifiers are designed and simulated. The simulation results are obtained at 1.2V supply voltage using Cadence EDA tool with 180nm GPDK technology file....
Nonetheless, efficient designs of the crossbar peripheral circuitry and I/O converters will be of ut- most importance to ensure that the computational memory unit meets those specifications. Moreover, to assess the capability of computational mem- ory to compete with already existing low-precision ...
When a row is selected, all the cells in that row are active. In general, there may be more than one bit line, since many memory circuits use both the true and complement forms of the bit. The row decoder circuitry is a demultiplexer that drives one of the n row lines in the core...
compute precision and weight capacity. There is also substantial research effort aimed at improving the energy efficiency of the peripheral circuitry associated with the IMC cores. The overall system-level architecture of a multi-core IMC chip as well as the appropriate communication fabric is being ...
Here we report a 2 Mb nvCIM macro (which combines memory cells and related peripheral circuitry) that is based on single-level cell resistive random-access memory devices and is fabricated in a 22 nm complementary metal–oxide–semiconductor foundry process. Compared with previous nvCIM ...
Peripheral circuitry, such as sense amplifiers and write drivers are shared among blocks. Despite similarities to conventional memory array architec- tures, PCM-specific design issues must be addressed. Choice of bitline sense amplifiers affect the read access time of the array. Voltage sense ...
7. In the chip of the invention--as in other dRAM chips--it is necessary to provide on the chip both nMOS and pMOS transistors arranged complementarily; not as part of the cells, but as part of the peripheral circuitry. If the chip has a p-substrate, then it is a simple matter to...
Meanwhile, the n-channel type MOSFETs used in the CMOS circuits constituting peripheral circuitry such as the X decoder, Y decoder or the like is formed in a p-type well region which is independent of the aforementioned common p-type well region M-WELL for the memory cell. In this ...
When receiving a pulse signal SG2 of level HIGH from the inverter circuit 308j as well as the output signal φE of level HIGH, the NAND circuit 307c provides a pulse signal of level LOW. Then, an inverter circuit 308k provides a CBR decision circuit 306 in a DRAM peripheral circuitry (...