US5359538 Aug 20, 1991 Oct 25, 1994 Vlsi Technology, Inc. Method for regular placement of data path components in VLSI circuitsUS5359538 * 1991年8月20日 1994年10月25日 Vlsi Technology, Inc. Method for regular placemen
A significant portion of the power in high performance CMOS VLSI circuits is dissipated in busses or global communications (Mehendaleet al., 1998;Winzker, 1998). Global communication typically involves the switching of largecapacitive loads, such asI/Oports and theclock distribution network, that...
Searched Keyword: VLSI. Part #: AVXX16. Datasheet: 249Kb/9P. Description: single-chip synthesizing CMOS VLSI. Manufacturer: Aplus Intergrated Circuits. 4 Results. Part #: AVXXX-TGX8. Datasheet: 269Kb/13P. Manufacturer: Aplus Intergrated Circuits.
SRC has the same limitations as a simple decimation sample rate control in terms of MCLK jitter. The sensitivity of ADC performance to clock jitter because of high fsin needs to be addressed by planning isolation barrier or noise filtering circuits on the MCLK. This challenge further scales up...
(VLSI) Complementary metal oxide (CMOS) circuits. The design of the CMOS circuits was implemented as a neural network with each neuron representing a CMOS cell. Later works like (Gobovic and Zaghloul1994; Yentis and Zaghloul1994,1996) used local neural networks for obtaining solutions of ...
(VLSI—Very Large Scale Integration). The introduction of the normalized Laplacian, in algorithms such as the SM, NJW, and self-tuning proved successful in image segmentation and general-purpose data analysis [108]. Some algorithms have been designed to handle very specific tasks such as the ...
A 1.5 v Circuit Technology for 64 Mb DRAMs, Nakagome et al., 1990 Symposium on VLSI Circuits, pp. 17-18. Primary Examiner: TRAN, ANDREW Q Attorney, Agent or Firm: ROBERT E. BUSHNELL Claims: What is claimed is: 1. A data transmission circuit for use in a semiconductor memory device ...
VLSI circuit CAD delays digital integrated circuits logic CAD timing RTL data path structure back-annotation controller costs execution times 会议名称: VLSI Design, 1997. Proceedings., Tenth International Conference on 会议时间: 1997/02/04 主办单位: IEEE ...
A circuit means for detecting data errors in VLSI processing circuits at the earliest point such an error occurs in the processing stream or (in different modes) at any selected point therein, and for providing the prior operands and faulty (intermediate) output data together with an indication ...
1. A VLSI circuit having a built-in test and maintenance system and wherein essentially all of the signal inputs and outputs go through unit I/O cells comprising: output buffer means, connected to provide output from the on-chip circuits to chip pins; ...