This work presents a low-power 50percent duty cycle corrector. A single-ended structure is adopted. The gain-boosting charge pump raises the loop performance and decreases the voltage ripples for increasing accuracy. The input duty range and operational frequency range are increased. The parameters ...
and experimental results of a battery charger composed of a cascaded boost and buck converter operating as a low THDi power factor corrector, which from a detailed loss analysis, develops a loss mitigation strategy that finds an adequate range of duty cycles combination of the converters that allow...
IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE A 500MHz DLL with Second Order Duty Cycle Corrector for Low JitterIEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE A 500MHz DLL with Second Order Duty Cycle Corrector for Low JitterKim, ByunggukOh...
18. The apparatus of claim 17 wherein the first DC-DC switching power converter comprises a double-clamped buck-boost converter and the controller is configured to control the duration of an energy storage phase within a converter operating cycle to increase in proportion to an increase in the ...
Provided is a duty cycle corrector including a low frequency detector detecting whether an input clock signal frequency is less than or greater than a predetermined frequency. If le
Reduction in the number of delay cells and use of low-power 50% duty cycle corrector can cause low output jitter and reduce power consumption. The overall power consumption of the system is 3.01 mW at a frequency of 1 GHz in the fast-locking situation with 1.2 V power supply, which ...
low-power electronicsADDCCCMOS processFS process cornerPVTIn this paper, a low-power delay-recycled all-digital duty-cycle corrector (ADDCC) is presented. The proposed ADDCC corrects the duty-cycle of the distorted clock to 50% under process, voltage, and temperature (PVT) variations. Besides...
Duty cycle corrector (DCC)Low jitterSDRAMA low-power low-jitter delay locked loop (DLL) with a first order differential closed-loop duty cycle corrector (DCC) is presented in this paper. The proposed DCC has a differential closed-loop struct...
direct data communication; modulated data communication; power level of signaling per line of the bus; voltage/current level for a data coding scheme per line (e.g., function of signal to noise ratio, power level, and data rate); number of lines in the bus; and a number of lines of ...
Long, S.Zhang, M.Ji, X.IEICE TRANSACTIONS ON ELECTRONICS E SERIES CD. Zheng-Chang , W. Jian-Hui , L. Shan-Li , Z. Meng and J. Xin-Cun "Duty cycle corrector for pipelined ADC with low added jitter", IEICE Trans. Electron. , vol. E92.C, no. 6, pp.864 ...