This work presents a low-power 50percent duty cycle corrector. A single-ended structure is adopted. The gain-boosting charge pump raises the loop performance and decreases the voltage ripples for increasing accuracy. The input duty range and operational frequency range are increased. The parameters ...
A wide range, low jitter Duty Cycle Corrector (DCC) based on continuous-time integrator is proposed. It introduces little added jitter in the sampling edge, which make it good candidate for pipelined ADC application. The circuit is implemented in CMOS 0.35m 2P4M Mixed Signal process. The experi...
IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE A 500MHz DLL with Second Order Duty Cycle Corrector for Low JitterIEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE A 500MHz DLL with Second Order Duty Cycle Corrector for Low JitterKim, ByunggukOh...
Reduction in the number of delay cells and use of low-power 50% duty cycle corrector can cause low output jitter and reduce power consumption. The overall power consumption of the system is 3.01 mW at a frequency of 1 GHz in the fast-locking situation with 1.2 V power supply, which ...
If less than, a common mode control circuit controlling a common mode of a duty cycle correction amplifier amplifying the input clock signal is disabled. The duty cycle corrector may include a column address strobe (CAS) latency determination unit that determines whether a CAS latency is greater ...
PURPOSE: A duty cycle corrector capable of preventing excessive duty cycle correction in low frequency is provided to prevent the excessive increase of variation amount of common mode by disabling a common mode control circuit.;CONSTITUTION: A duty cycle correction amplifier(31) amplifies the ...
Duty cycle corrector (DCC)Low jitterSDRAMA low-power low-jitter delay locked loop (DLL) with a first order differential closed-loop duty cycle corrector (DCC) is presented in this paper. The proposed DCC has a differential closed-loop struct...
Disclosed is a duty cycle corrector including a buffer circuit, an upper circuit, and a lower circuit. The buffer circuit includes: a first buffer circuit receiving a first input signal and thereby outputting a second output signal to a second output terminal; a second buffer circuit receiving ...
A novel realignment duty cycle corrector (RDCC) is proposed for the DLL. The RDCC circuit can make the output waveform of the DLL maintain a 50% duty cycle in a lock mode. The RDCC circuit has advantages of low power consumption, small chip area and high operating frequency. The proposed...
Disclosed is a duty cycle corrector including a buffer circuit, an upper circuit, and a lower circuit. The buffer circuit includes: a first buffer circuit receiving a first input signal and thereby outputting a second output signal to a second output terminal; a second buffer circuit receiving ...