A duty-cycle correction (DCC) circuit adapted to adjust the duty cycle of a differential clock signal to conform it to the requirements of a half-rate clocking system. In a representative embodiment, the DCC circuit has a buffer circuit adapted to generate a differential output clock signal by...
A duty-cycle correction circuit may include a delayed clock generation unit suitable for generating a plurality of delayed clocks by delaying a target clock by different delay values, an up/down signal generation unit suitable for selecting a delayed clock having a delay value corresponding to a ...
Duty-cycle correction circuit 专利名称：Duty-cycle correction circuit 发明人：Raj Mahadevan,Tony Pialis 申请号：US11129996 申请日：20050516 公开号：US20050253637A1 公开日：20051117 专利内容由知识产权出版社提供 专利附图：摘要：A duty-cycle correction (DCC) circuit adapted to adjust the duty cycle of...
A duty cycle correction circuit is provided to use various duty cycles selectively by using a MUX switch. A T- FF(Toggle Flip-Flop) unit(110) outputs a duty cycle signal with 2T cycle for the duty cycle of an input signal. A DLL unit(120) matches the synchronization of an input signal...
DUTY CYCLE CORRECTION CIRCUIT AND DUTY CYCLE CORRECTION METHOD A duty cycle correction circuit may include: a phase mixing section capable of mixing a first integrated signal generated by integrating a positive clock signal, with a first compensation signal generated by differentiating and integrati.....
专利名称：Duty cycle correction circuit of delay locked loop and delay locked loop having the duty cycle correction circuit 发明人：Chan-kyung Kim 申请号：US11512155 申请日：20060830 公开号：US20060290397A1 公开日：20061228 专利内容由知识产权出版社提供 专利附图：摘要：A duty cycle correction circuit...
A control circuit corrects duty-cycle distortion of clock signals accurately and with a fast and continuous response over a wide dynamic range. In one embodiment, the duty-cycle correction circuit inc
专利名称:Duty-cycle correction circuit and method 发明人:Yo-Han Jeong 申请号:US15651111 申请日:20170717 公开号:US10090828B2 公开日:20181002 专利附图: 摘要:A duty-cycle correction circuit may include a delayed clock generation unit suitable for generating a plurality of delayed clocks by delaying ...
A duty cycle correction circuit for a semiconductor memory device capable of exchanging data on both edges of rising and falling of clock by correcting duty error of input clock signal by using a multi phase signal generator. The circuit comprises: a phase detection unit for receiving an input ...
Open-loop full-digital duty cycle correction circuit The duty cycle of the clock is corrected to be 50% by an open-loop full-digital duty cycle correction (DCC) circuit. Due to its open-loop and full-digital ... C Yoo,C Jeong,J Kih - 《Iee Electron Lett》 被引量: 42发表: 2005年...