The pin then becomes a very high impedance node and is, therefore, sensitive to noise pickup and PCB leakage currents. GND This pin must be connected to system ground for the DRV103 to function. It carries the 0.4mA quiescent current plus the full load current when the power DMOS ...
8.3.6 Latch-Up Immune Latch-Up is a condition where a low impedance path is created between a supply pin and ground. This condition is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains even after the trigger is no longer present. ...
This low impedance path may cause system upset or catastrophic damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the low impedance path. The TMUX721x family of devices are constructed on silicon on insulator (SOI) based process where an...
This low impedance path may cause system upset or catastrophic damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the low impedance path. The TMUX721x family of devices are constructed on silicon on insulator (SOI) based process where an...
Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling...