Leakage Current in DRAM Memory Cell 来自 Semantic Scholar 喜欢 0 阅读量: 140 作者: J Yu,K Aflatooni 摘要: Retention time is a critical characteristic in dynamic random access memory (DRAM) design. In order to improve DRAM retention time characteristics, leakage current must be reduced and ...
Dynamic random access memories (DRAMs) are devices where a large amount of information can be bit-wise stored by writing a certain amount of charge into a particular memory cell. A DRAM device contains a large number of these memory cells, which consist of only two separate device structures:...
The power consumption of capacitor leakage current, increase of the capacitor aspect ratio, and lack of higher dielectric constant (κ) material are the difficult challenges to downscaling dynamic random access memory (DRAM). This letter reports a new one-transistor ferroelectric-MOSFET (1T FeMOS) ...
A CMOS integrated circuit (e.g., an SRAM or a DRAM) is partitioned into a core block, a peripheral block, and a retention block. The core block includes circuits (e.g., memory cells) that are powered on at all times and is coupled directly to power supply and circuit ground. The ...
Leakage Current in DRAM Memory Cell Retention time is a critical characteristic in dynamic random access memory (DRAM) design. In order to improve DRAM retention time characteristics, leakage... J Yu,K Aflatooni - IEEE 被引量: 6发表: 2006年 ...
Leakage-current reduction in thin Ta\\/sub 2\\/O\\/sub 5\\/ films for high-density VLSI memories C Hashimoto,H Oikawa,N Honma - 《IEEE Trans Electron Devices》 被引量: 41发表: 1989年 Leakage-current reduction in thin Ta2O5 films for high-density VLSI memories "Leakage Current ...
A circuit and a method for self refresh of DRAM cells are provided. The circuit comprises a bias generator and an oscillator. The bias generator comprises a first current generator, a second current generator and a converter. The first current generator generates a first leakage current of "0"...
This work proposes a new test algorithm for detecting bit line disturbed weak cells in dynamic random access memory (DRAM). The basic idea of the proposed test algorithm is to test using the voltage difference between the storage node and the bit line during the read operation of the first ...
Two-Transistor Floating-Body Dynamic Memory Cell Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better sign... JG ...
To reduce gate-induced drain leakage in DRAM word lines PROBLEM TO BE SOLVED: To provide a dynamic random access memory cell having a buried word line with reduced gate-induced drain leakage. A memory device inc... カン, スンクォン,リー, キルヨン,ユ, サン ホ,... 被引量: 0发表:...