We also refer to isolation cells in VLSI as clamp cells. An isolation cell is necessary for low-power architecture when each logic signal passes from a power domain that can be turned down to a domain that canno
Shirota “A Novel Self-Aligned Shallow Trench Isolation Cell for 90nm 4Gbit NAND Flash EEPROMs” in Symp.VLSI Circuits Dig. Tech. Papers, pp. 212-213, Jun. 2003Ichige, M., et al., " A Novel Self-Aligned Shallow Trench Isolation Cell for 90nm 4Gbit NAND Flash EEPROMs, " Symposium ...
Horii, H. et al., “A Novel Cell Technology Using N-doped GeSbTe Films for Phase Change RAM,” 2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 177-178. Hwang, Y. N. et al., “Full Integration and Reliability Evaluation of Phase-change RAM Based on 0.24 μm-CMOS ...
5485031Antifuse structure suitable for VLSI application1996-01-16Zhang et al. 5469393Circuit and method for decreasing the cell margin during a test mode1995-11-21Thomann 5457659Programmable dynamic random access memory (DRAM)1995-10-10Schaefer ...
We have integrated a high speed and high density 6T-SRAM cell (0.998 渭m2) for system-on-a-chip (SOC) using enhanced 100 nm CMOS logic technology. This is ... K Tomita,K Hashimoto,T Inbe,... - 《Vlsi Tech Dig》 被引量: 8发表: 2002年 Method of fabricating a shallow trench is...
Application of a two-layer planarization process to VLSI intermetal dielectric and trench isolation processesAnimalsMice, Inbred BALB CHumansMiceCell LineSalmonella enteritidisDisease Models, AnimalCaspasesBacterial ProteinsNF-kappa BMany important bacterial virulence factors act as mimics of mammalian proteins...
This phenomenon strongly increases the threshold voltage fluctuation of cell transistors depending on the junction biases of neighboring cell transistors and will impose physical size and the voltage scaling constraints for the Gigabit level DRAM technology.Jai-Hoon Sim...
structure, including word lines (i.e., gate regions) and bit lines (i.e., source/drain regions), thus increasing the cell ratio of channel width of cell transistor to that of pass transistor to keep the data stored in the cell transistor more stable without increasing the area per cell....
The measurement results show only 0.4-dB gain degradation in a 5-GHz amplifier with a boundary-scan cell and LC isolation networks.doi:10.1109/vtest.2004.1299263Tian-Wei HuangPei-Si WuRen-Chieh LiuJeng-Han TsaiHuei WangTzi-Dar ChiuehVLSI Test Symposium, 2004. Proceedings. 22nd IEEEHuang, Wu,...
5420061Method for improving latchup immunity in a dual-polysilicon gate process1995-05-30Manning437/57 5416348Current leakage reduction at the storage node diffusion region of a stacked-trench DRAM cell by selectively oxidizing the floor of the trench1995-05-16Jeng257/297 ...