Theinsidekeyword in SystemVerilog allows to check if a given value lies within the range specified using theinsidephrase. This can also be used insideifand other conditional statements in addition to being used as a constraint. Syntax <variable>inside{<valuesorrange>}// Inverted "inside"!(<var...
Using the "inside" keyword with a "case" block to enable the definition of ranges for a desired output value in systemverilog code (cf. attached example) synthesis fails on an apparent syntax error. Result Error (10170): Verilog HDL syntax error at frontend_ifc.sv(370)...