Exercise 4.25 Sketch the state transition diagram for the FSM described by the following HDL code. An FSM of this nature is used in a branch predictor on some microprocessors. SystemVerilog module fsm1(input lo
This paper describes analysis of on-chip bus power in the presence of arrival time variations of input signals. With shrinking process geometries, coupling power between neighboring bus lines has enlarged. The coupling power depends on not only signal transition type but also the relative signal ...
Marginal triggering and metastable behavior together with their consequences are also examined in detail. It turns out that the mean time between errors (MTBE) of a synchronizer almost entirely depends on the data rates and clock frequencies involved. View chapter Book 2015, Top-Down Digital VLSI ...
time, devices that are not supposed to switch should see small voltage drops only for a limited amount of time. One consequence is that multi-input gates with a large difference in the number of inputs cannot be used with the same clocking scheme. The nonlinearity of the switching kinetics ...
Rodriguez R, Lánský P (2000) Effect of spatial extension on noise-enhanced phase locking in a leaky integrate-and-fire model of a neuron. Phys Rev E 62:1–11 Google Scholar Sakaguchi H (2004) Oscillatory phase transition and pulse propagation in noisy integrate-and-fire neurons. Phys Rev...
[4] F. Najm, "Transition density: A new measure of activity in digital circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 12, no. 2, pp. 310–323, Feb. 1993. [5] Farid N. Najm, , "A Survey of Power Estimation Techniques in VLSI Circuits" IEEE transactions...
(see FIG. 2). The elements of IBIS model 1700 comprise pulldown transistor 1710, pull-up transistor 1720, transition time characteristics 1730, DC I/V characteristics of clamping diodes 1740, and parasitic characteristics 1750. Parasitic characteristics 1750 comprises output pad capacitance 1751, ...
In order to create a transition at the output of the Launch DFF 610, the IW-D 600 uses an inverter 640 and MUX 650 feeding back the Launch register output to its input. The Launch register 610 is initialized by transferring a 0 or 1 to its input through the I/O soft wrapper and ...
in a first input-output circuit, where the first input-output circuit is part of the first group of input-output circuits that are being determined at the same time, and a second delay test path includes the launch bus and the capture strobe bus through a second launch register to a ...
A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the ...