This paper describes analysis of on-chip bus power in the presence of arrival time variations of input signals. With shrinking process geometries, coupling power between neighboring bus lines has enlarged. The coupling power depends on not only signal transition type but also the relative signal ...
Exercise 4.25 Sketch the state transition diagram for the FSM described by the following HDL code. An FSM of this nature is used in a branch predictor on some microprocessors. SystemVerilog module fsm1(input logic clk, reset, input logic taken, back, output logic predicttaken); logic [4:0...
Rodriguez R, Lánský P (2000) Effect of spatial extension on noise-enhanced phase locking in a leaky integrate-and-fire model of a neuron. Phys Rev E 62:1–11 Google Scholar Sakaguchi H (2004) Oscillatory phase transition and pulse propagation in noisy integrate-and-fire neurons. Phys Rev...
time, devices that are not supposed to switch should see small voltage drops only for a limited amount of time. One consequence is that multi-input gates with a large difference in the number of inputs cannot be used with the same clocking scheme. The nonlinearity of the switching kinetics ...
Redman-White W (1997) A high bandwidth constant-gm and slew-rate rail-to-rail CMOS input circuit and its application to analog cells for low voltage VLSI systems. IEEE J Solid-State Circuits 32: 701–712 Article Google Scholar Wang M, Mayhugh TL Jr, Embabi SHK, Sanchez-Sinencio E (...
[4] F. Najm, "Transition density: A new measure of activity in digital circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 12, no. 2, pp. 310–323, Feb. 1993. [5] Farid N. Najm, , "A Survey of Power Estimation Techniques in VLSI Circuits" IEEE transactions...
The elements of IBIS model 1700 comprise pulldown transistor 1710, pull-up transistor 1720, transition time characteristics 1730, DC I/V characteristics of clamping diodes 1740, and parasitic characteristics 1750. Parasitic characteristics 1750 comprises output pad capacitance 1751, lead inductance 1752,...
by this time signals m and r have had two transitions while signals o and q have had a single transition. Now signal q falls (signal p was high), therefore signal n goes low and therefore signal r goes low. This causes signal o to go low. Thus, as has been described, whenever sign...
effect a negative peak detector, capturing the most negative value of at least one input level and holding that level, with a slow leakage of the held value back toward the upper voltage supply with a time constant that is generally set much slower than the input signal transition frequency....
inappropriate command or data output by the electronic device when a transition is made from test mode to normal operating mode. Thus, there is a need to provide an apparatus and a method for placing the electronic device into a safe internal logic state whenever any type of testing of core...