It reaches the MIG core and I want to write it to the memory. But somehow, the init_calib_complete always stays low and as the calibration is not over, I guess I do not get to perform read and write to the memory. The dq always stays into high impedence state. Is there anything ...
SIM_BYPASS_INIT_CAL : string := "FAST"; -- # = "OFF" - Complete memory init & -- calibration sequence -- # = "SKIP" - Not supported -- # = "FAST" - Complete memory init & use -- abbreviated calib sequence SIMULATION : string := "TRUE"; -- Should be TRUE during design sim...
1.3 CKE使能和ck_t/ck_c打开 1.4 MRS寄存器模式配置 二、Calibration 2.1 颗粒端ZQ Calibraton 2...
为了仿真激励的需要,需要将app_sr_req,app_ref_req,app_zq_req, 三个信号拉低,这也是模板里面唯一需要修改的地方。 mig_7series_0u_mig_7series_zyy(// Memory interface ports.ddr3_addr(ddr3_addr),// output [14:0] ddr3_addr.ddr3_ba(ddr3_ba),// output [2:0] ddr3_ba.ddr3_cas_n(d...
完全是mig生成的工程 仿真没有问题但是debug时init calib complete没有拉高 有没有人遇到过类似问题？
Hi, I created a DDR interface for KC705 using the XTP196 (KC705 MIG Design Creation) document and then I generted the MIG example design . I used Vivado simulator to simulate the exmple design and I can see the init_calib_